diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckWidths.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 44 |
2 files changed, 45 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 5ae5dad4..6ceac032 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -121,7 +121,7 @@ object CheckWidths extends Pass { errors append new BitsWidthException(info, target.serialize, hi, bitWidth(a.tpe), e.serialize) case DoPrim(Head, Seq(a), Seq(n), _) if (hasWidth(a.tpe) && bitWidth(a.tpe) < n) => errors append new HeadWidthException(info, target.serialize, n, bitWidth(a.tpe)) - case DoPrim(Tail, Seq(a), Seq(n), _) if (hasWidth(a.tpe) && bitWidth(a.tpe) <= n) => + case DoPrim(Tail, Seq(a), Seq(n), _) if (hasWidth(a.tpe) && bitWidth(a.tpe) < n) => errors append new TailWidthException(info, target.serialize, n, bitWidth(a.tpe)) case DoPrim(Dshl, Seq(a, b), _, _) if (hasWidth(a.tpe) && bitWidth(b.tpe) >= DshlMaxWidth) => errors append new DshlTooBig(info, target.serialize) diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index b7df945f..d2e2f295 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -20,6 +20,10 @@ class UnitTests extends FirrtlFlatSpec { } } + private def executeTest(input: String, expected: String, transforms: Seq[Transform]) = { + execute(input, transforms).circuit should be (parse(expected)) + } + def execute(input: String, transforms: Seq[Transform]): CircuitState = { val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, t: Transform) => t.runTransform(c) @@ -275,6 +279,26 @@ class UnitTests extends FirrtlFlatSpec { } } + "zero head select" should "return an empty module" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + ResolveFlows, + new InferWidths, + CheckWidths, + new DeadCodeElimination) + val input = + """circuit Unit : + | module Unit : + | node x = head(UInt(1), 0)""".stripMargin + val check = + """circuit Unit : + | module Unit : + | skip""".stripMargin + executeTest(input, check, passes) + } + "Oversized tail select" should "throw an exception" in { val passes = Seq( ToWorkingIR, @@ -294,6 +318,26 @@ class UnitTests extends FirrtlFlatSpec { } } + "max tail select" should "return an empty module" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + ResolveFlows, + new InferWidths, + CheckWidths, + new DeadCodeElimination) + val input = + """circuit Unit : + | module Unit : + | node x = tail(UInt(1), 1)""".stripMargin + val check = + """circuit Unit : + | module Unit : + | skip""".stripMargin + executeTest(input, check, passes) + } + "Partial connecting incompatable types" should "throw an exception" in { val passes = Seq( ToWorkingIR, |