diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala index 9bf4f779..40626765 100644 --- a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala +++ b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala @@ -44,6 +44,7 @@ class RemoveVerificationStatements extends Transform val newState = state.copy(circuit = run(state.circuit)) if (removedCounter > 0) { StageUtils.dramaticWarning(s"$removedCounter verification statements " + + "(assert, assume or cover) " + "were removed when compiling to Verilog because the basic Verilog " + "standard does not support them. If this was not intended, compile " + "to System Verilog instead using the `-X sverilog` compiler flag.") |