2 files changed, 3 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index ea0767bb..5c1b1a67 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -19,7 +19,7 @@ class CheckSpec extends FlatSpec with Matchers {
         |      depth => 32
         |      read-latency => 0
         |      write-latency => 1""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckHighForm.MemWithFlipException] {
       passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index dac8a40f..98693c61 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -60,12 +60,11 @@ class UnitTests extends FirrtlFlatSpec {
         |    input y: {a : UInt<1>}
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
-    val thrown = intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidConnect] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
-    assert(thrown.getMessage contains "Type mismatch. Cannot connect")
   }
 
   "Initializing a register with a different type" should "throw an exception" in {
@@ -83,7 +82,7 @@ class UnitTests extends FirrtlFlatSpec {
        |    wire x : { valid : UInt<1> }
        |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
        |      reset => (reset, x)""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidRegInit] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }