aboutsummaryrefslogtreecommitdiff
path: root/src/test
diff options
context:
space:
mode:
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala8
-rw-r--r--src/test/scala/firrtlTests/DCETests.scala5
-rw-r--r--src/test/scala/firrtlTests/FlattenTests.scala6
-rw-r--r--src/test/scala/firrtlTests/InfoSpec.scala4
-rw-r--r--src/test/scala/firrtlTests/RemoveWiresSpec.scala123
5 files changed, 136 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index e7bf7884..06e24b97 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -721,7 +721,13 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
| wire z : UInt<1>
| y <= z
| z <= x""".stripMargin
- val check = input
+ val check =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | output y : UInt<1>
+ | node z = x
+ | y <= z""".stripMargin
execute(input, check, Seq(dontTouch("Top.z")))
}
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index ea34d4be..d1848ab8 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -60,9 +60,8 @@ class DCETests extends FirrtlFlatSpec {
| module Top :
| input x : UInt<1>
| output z : UInt<1>
- | wire a : UInt<1>
- | z <= x
- | a <= x""".stripMargin
+ | node a = x
+ | z <= x""".stripMargin
exec(input, check, Seq(dontTouch("Top.a")))
}
"Unread register" should "be deleted" in {
diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala
index 10988f8f..570d03bf 100644
--- a/src/test/scala/firrtlTests/FlattenTests.scala
+++ b/src/test/scala/firrtlTests/FlattenTests.scala
@@ -64,9 +64,8 @@ class FlattenTests extends LowTransformSpec {
| output b : UInt<32>
| inst i1 of Inline1
| inst i2 of Inline1
- | wire tmp : UInt<32>
| i1.a <= a
- | tmp <= i1.b
+ | node tmp = i1.b
| i2.a <= tmp
| b <= i2.b
| module Inline1 :
@@ -84,9 +83,8 @@ class FlattenTests extends LowTransformSpec {
| wire i2$a : UInt<32>
| wire i2$b : UInt<32>
| i2$b <= i2$a
- | wire tmp : UInt<32>
+ | node tmp = i1$b
| b <= i2$b
- | tmp <= i1$b
| i1$a <= a
| i2$a <= tmp
| module Inline1 :
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 4cb25640..8d49d753 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -59,8 +59,8 @@ class InfoSpec extends FirrtlFlatSpec {
)
result should containTree { case DefRegister(Info1, "r", _,_,_,_) => true }
result should containLine (s"reg [7:0] r; //$Info1")
- result should containTree { case DefWire(Info2, "w", _) => true }
- result should containLine (s"wire [7:0] w; //$Info2")
+ result should containTree { case DefNode(Info2, "w", _) => true }
+ result should containLine (s"wire [7:0] w; //$Info2") // Node "w" declaration in Verilog
result should containTree { case DefNode(Info3, "n", _) => true }
result should containLine (s"wire [7:0] n; //$Info3")
result should containLine (s"assign n = w | x; //$Info3")
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
new file mode 100644
index 00000000..cfc03ad9
--- /dev/null
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -0,0 +1,123 @@
+// See LICENSE for license details.
+
+package firrtlTests
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Mappers._
+import FirrtlCheckers._
+
+import collection.mutable
+
+class RemoveWiresSpec extends FirrtlFlatSpec {
+ def compile(input: String): CircuitState =
+ (new LowFirrtlCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
+ def compileBody(body: String) = {
+ val str = """
+ |circuit Test :
+ | module Test :
+ |""".stripMargin + body.split("\n").mkString(" ", "\n ", "")
+ compile(str)
+ }
+
+ def getNodesAndWires(circuit: Circuit): (Seq[DefNode], Seq[DefWire]) = {
+ require(circuit.modules.size == 1)
+
+ val nodes = mutable.ArrayBuffer.empty[DefNode]
+ val wires = mutable.ArrayBuffer.empty[DefWire]
+ def onStmt(stmt: Statement): Statement = {
+ stmt map onStmt match {
+ case node: DefNode => nodes += node
+ case wire: DefWire => wires += wire
+ case _ =>
+ }
+ stmt
+ }
+
+ circuit.modules.head match {
+ case Module(_,_,_, body) => onStmt(body)
+ }
+ (nodes, wires)
+ }
+
+ "Remove Wires" should "turn wires and their single connect into nodes" in {
+ val result = compileBody(s"""
+ |input a : UInt<8>
+ |output b : UInt<8>
+ |wire w : UInt<8>
+ |w <= a
+ |b <= w""".stripMargin
+ )
+ val (nodes, wires) = getNodesAndWires(result.circuit)
+ wires.size should be (0)
+
+ nodes.map(_.serialize) should be (Seq("node w = a"))
+ }
+
+ it should "order nodes in a legal, flow-forward way" in {
+ val result = compileBody(s"""
+ |input a : UInt<8>
+ |output b : UInt<8>
+ |wire w : UInt<8>
+ |wire x : UInt<8>
+ |node y = x
+ |x <= w
+ |w <= a
+ |b <= y""".stripMargin
+ )
+ val (nodes, wires) = getNodesAndWires(result.circuit)
+ wires.size should be (0)
+ nodes.map(_.serialize) should be (
+ Seq("node w = a",
+ "node x = w",
+ "node y = x")
+ )
+ }
+
+ it should "properly pad rhs of introduced nodes if necessary" in {
+ val result = compileBody(s"""
+ |output b : UInt<8>
+ |wire w : UInt<8>
+ |w <= UInt(2)
+ |b <= w""".stripMargin
+ )
+ val (nodes, wires) = getNodesAndWires(result.circuit)
+ wires.size should be (0)
+ nodes.map(_.serialize) should be (
+ Seq("""node w = pad(UInt<2>("h2"), 8)""")
+ )
+ }
+
+ it should "support arbitrary expression for wire connection rhs" in {
+ val result = compileBody(s"""
+ |input a : UInt<8>
+ |input b : UInt<8>
+ |output c : UInt<8>
+ |wire w : UInt<8>
+ |w <= tail(add(a, b), 1)
+ |c <= w""".stripMargin
+ )
+ val (nodes, wires) = getNodesAndWires(result.circuit)
+ wires.size should be (0)
+ nodes.map(_.serialize) should be (
+ Seq("""node w = tail(add(a, b), 1)""")
+ )
+ }
+
+ it should "do a reasonable job preserving input order for unrelatd logic" in {
+ val result = compileBody(s"""
+ |input a : UInt<8>
+ |input b : UInt<8>
+ |output z : UInt<8>
+ |node x = not(a)
+ |node y = not(b)
+ |z <= and(x, y)""".stripMargin
+ )
+ val (nodes, wires) = getNodesAndWires(result.circuit)
+ wires.size should be (0)
+ nodes.map(_.serialize) should be (
+ Seq("node x = not(a)",
+ "node y = not(b)")
+ )
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 17:49:09 +0000