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-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index af186cda..ef52507f 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1148,6 +1148,31 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
execute(input, check, Seq.empty)
}
+ "Const prop of registers" should "do limited speculative expansion of optimized muxes to absorb bigger cones" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input clock : Clock
+ | input en : UInt<1>
+ | output out : UInt<1>
+ | reg r1 : UInt<1>, clock
+ | reg r2 : UInt<1>, clock
+ | when en :
+ | r1 <= UInt<1>(1)
+ | r2 <= UInt<1>(0)
+ | when en :
+ | r2 <= r2
+ | out <= xor(r1, r2)""".stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | input clock : Clock
+ | input en : UInt<1>
+ | output out : UInt<1>
+ | out <= UInt<1>("h1")""".stripMargin
+ execute(input, check, Seq.empty)
+ }
+
"A register with constant reset and all connection to either itself or the same constant" should "be replaced with that constant" in {
val input =
"""circuit Top :