diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/WiringTests.scala | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 5dd048a3..6da73157 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -395,17 +395,13 @@ class WiringTests extends FirrtlFlatSpec { } it should "wire with source and sink in the same module" in { - val sinks = Seq(ComponentName("s", ModuleName("A", CircuitName("Top")))) - val source = ComponentName("r", ModuleName("A", CircuitName("Top"))) + val sinks = Seq(ComponentName("s", ModuleName("Top", CircuitName("Top")))) + val source = ComponentName("r", ModuleName("Top", CircuitName("Top"))) val sas = WiringInfo(source, sinks, "pin") val input = """|circuit Top : | module Top : | input clock: Clock - | inst a of A - | a.clock <= clock - | module A : - | input clock: Clock | wire s: UInt<5> | reg r: UInt<5>, clock |""".stripMargin @@ -413,10 +409,6 @@ class WiringTests extends FirrtlFlatSpec { """|circuit Top : | module Top : | input clock: Clock - | inst a of A - | a.clock <= clock - | module A : - | input clock: Clock | wire pin: UInt<5> | wire s: UInt<5> | reg r: UInt<5>, clock |