diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/CompilerTests.scala | 32 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/DriverSpec.scala | 8 |
2 files changed, 38 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index 348ed300..dc70847a 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -13,6 +13,7 @@ import firrtl.{ Compiler, HighFirrtlCompiler, MiddleFirrtlCompiler, + MinimumVerilogCompiler, LowFirrtlCompiler, Parser, VerilogCompiler @@ -153,3 +154,34 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers { getOutput should be (check) } } + +class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers { + val input = """|circuit Top: + | module Top: + | output b: UInt<1>[3] + | node c = bits(UInt<3>("h7"), 2, 2) + | node d = shr(UInt<3>("h7"), 2) + | b[0] is invalid + | b[1] <= c + | b[2] <= d + |""".stripMargin + val check = """|module Top( + | output b_0, + | output b_1, + | output b_2 + |); + | wire c; + | wire d; + | assign c = 1'h1; + | assign d = 1'h1; + | assign b_0 = 1'h0; + | assign b_1 = c; + | assign b_2 = d; + |endmodule + |""".stripMargin + def compiler = new MinimumVerilogCompiler() + + "A circuit's minimum Verilog output" should "not have constants propagated or dead code eliminated" in { + getOutput should be (check) + } +} diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index 545bf09a..ae1e08e7 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -371,7 +371,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> "./Top.lo.fir", "high" -> "./Top.hi.fir", "middle" -> "./Top.mid.fir", - "verilog" -> "./Top.v" + "verilog" -> "./Top.v", + "mverilog" -> "./Top.v", + "sverilog" -> "./Top.sv" ).foreach { case (compilerName, expectedOutputFileName) => val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { commonOptions = CommonOptions(topName = "Top") @@ -391,7 +393,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> Seq("./Top.lo.fir", "./Child.lo.fir"), "high" -> Seq("./Top.hi.fir", "./Child.hi.fir"), "middle" -> Seq("./Top.mid.fir", "./Child.mid.fir"), - "verilog" -> Seq("./Top.v", "./Child.v") + "verilog" -> Seq("./Top.v", "./Child.v"), + "mverilog" -> Seq("./Top.v", "./Child.v"), + "sverilog" -> Seq("./Top.sv", "./Child.sv") ).foreach { case (compilerName, expectedOutputFileNames) => println(s"$compilerName -> $expectedOutputFileNames") val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { |