2 files changed, 64 insertions, 12 deletions

diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
index 24793437..63def26a 100644
--- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
@@ -165,10 +165,14 @@ trait FirrtlRunners extends BackendCompilationUtilities {
 
   /** Compiles input Firrtl to Verilog */
   def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = {
+    compileToVerilogCircuitState(input, annotations).getEmittedCircuit.value
+  }
+
+  /** Compiles input Firrtl to Verilog */
+  def compileToVerilogCircuitState(input: String, annotations: AnnotationSeq = Seq.empty): CircuitState = {
     val circuit = Parser.parse(input.split("\n").toIterator)
     val compiler = new VerilogCompiler
-    val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations), extraCheckTransforms)
-    res.getEmittedCircuit.value
+    compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations), extraCheckTransforms)
   }
 
   /** Compile a Firrtl file
diff --git a/src/test/scala/firrtlTests/InlineCastsSpec.scala b/src/test/scala/firrtlTests/InlineCastsSpec.scala
index e27020e5..7a248def 100644
--- a/src/test/scala/firrtlTests/InlineCastsSpec.scala
+++ b/src/test/scala/firrtlTests/InlineCastsSpec.scala
@@ -4,18 +4,19 @@ package firrtlTests
 
 import firrtl.transforms.InlineCastsTransform
 import firrtl.testutils.FirrtlFlatSpec
+import firrtl.testutils.FirrtlCheckers._
 
-/*
- * Note: InlineCasts is still part of mverilog, so this test must both:
- * - Test that the InlineCasts fix is effective given the current mverilog
- * - Provide a test that will be robust if and when InlineCasts is no longer run in mverilog
- *
- * This is why the test passes InlineCasts as a custom transform: to future-proof it so that
- * it can do real LEC against no-InlineCasts. It currently is just a sanity check that the
- * emitted Verilog is legal, but it will automatically become a more meaningful test when
- * InlineCasts is not run in mverilog.
- */
 class InlineCastsEquivalenceSpec extends FirrtlFlatSpec {
+  /*
+   * Note: InlineCasts is still part of mverilog, so this test must both:
+   * - Test that the InlineCasts fix is effective given the current mverilog
+   * - Provide a test that will be robust if and when InlineCasts is no longer run in mverilog
+   *
+   * This is why the test passes InlineCasts as a custom transform: to future-proof it so that
+   * it can do real LEC against no-InlineCasts. It currently is just a sanity check that the
+   * emitted Verilog is legal, but it will automatically become a more meaningful test when
+   * InlineCasts is not run in mverilog.
+   */
   "InlineCastsTransform" should "not produce broken Verilog" in {
     val input =
       s"""circuit literalsel_fir:
@@ -26,4 +27,51 @@ class InlineCastsEquivalenceSpec extends FirrtlFlatSpec {
          |""".stripMargin
     firrtlEquivalenceTest(input, Seq(new InlineCastsTransform))
   }
+
+  it should "not inline complex expressions into other complex expressions" in {
+    val input =
+      """circuit NeverInlineComplexIntoComplex :
+        |  module NeverInlineComplexIntoComplex :
+        |    input a : SInt<3>
+        |    input b : UInt<2>
+        |    input c : UInt<2>
+        |    input sel : UInt<1>
+        |    output out : SInt<3>
+        |    node diff = sub(b, c)
+        |    out <= mux(sel, a, asSInt(diff))
+        |""".stripMargin
+    val expected =
+      """module NeverInlineComplexIntoComplexRef(
+        |  input  [2:0] a,
+        |  input  [1:0] b,
+        |  input  [1:0] c,
+        |  input        sel,
+        |  output [2:0] out
+        |);
+        |  wire [2:0] diff = b - c;
+        |  assign out = sel ? $signed(a) : $signed(diff);
+        |endmodule
+        |""".stripMargin
+    firrtlEquivalenceWithVerilog(input, expected)
+  }
+
+  it should "inline casts on both sides of a more complex expression" in {
+    val input =
+      """circuit test :
+        |  module test :
+        |    input clock : Clock
+        |    input in : UInt<8>
+        |    output out : UInt<8>
+        |
+        |    node _T_1 = asUInt(clock)
+        |    node _T_2 = not(_T_1)
+        |    node clock_n = asClock(_T_2)
+        |    reg r : UInt<8>, clock_n
+        |    r <= in
+        |    out <= r
+        |""".stripMargin
+    val verilog = compileToVerilogCircuitState(input)
+    verilog should containLine("always @(posedge clock_n) begin")
+
+  }
 }