diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/InfoSpec.scala | 71 |
1 files changed, 69 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala index 01e0a0ac..a2410f9d 100644 --- a/src/test/scala/firrtlTests/InfoSpec.scala +++ b/src/test/scala/firrtlTests/InfoSpec.scala @@ -23,6 +23,7 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { val Info1 = FileInfo(StringLit("Source.scala 1:4")) val Info2 = FileInfo(StringLit("Source.scala 2:4")) val Info3 = FileInfo(StringLit("Source.scala 3:4")) + val Info4 = FileInfo(StringLit("Source.scala 4:4")) "Source locators on module ports" should "be propagated to Verilog" in { val result = compileBody(s""" @@ -119,6 +120,21 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { result should containLine (s"Child c ( //$Info1") } + it should "be propagated across direct node assignments and connections" in { + val result = compile(s""" + |circuit Test : + | module Test : + | input in : UInt<8> + | output out : UInt<8> + | node a = in $Info1 + | node b = a + | out <= b + |""".stripMargin + ) + result should containTree { case Connect(Info1, Reference("out", _,_,_), Reference("in", _,_,_)) => true } + result should containLine (s"assign out = in; //$Info1") + } + "source locators" should "be propagated through ExpandWhens" in { val input = """ |;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.7, sbtVersion: 0.13.11, builtAtString: 2016-11-26 18:48:38.030, builtAtMillis: 1480186118030 @@ -155,8 +171,12 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { """.stripMargin val result = (new LowFirrtlCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty) - result should containLine ("x <= _GEN_2 @[GCD.scala 17:22 GCD.scala 19:19]") - result should containLine ("y <= _GEN_3 @[GCD.scala 18:22 GCD.scala 19:30]") + result should containLine ("node _GEN_0 = mux(_T_14, _T_16, x) @[GCD.scala 17:18 GCD.scala 17:22 GCD.scala 15:14]") + result should containLine ("node _GEN_2 = mux(io_e, io_a, _GEN_0) @[GCD.scala 19:15 GCD.scala 19:19]") + result should containLine ("x <= _GEN_2") + result should containLine ("node _GEN_1 = mux(_T_18, _T_20, y) @[GCD.scala 18:18 GCD.scala 18:22 GCD.scala 16:14]") + result should containLine ("node _GEN_3 = mux(io_e, io_b, _GEN_1) @[GCD.scala 19:15 GCD.scala 19:30]") + result should containLine ("y <= _GEN_3") } "source locators for append option" should "use multiinfo" in { @@ -173,6 +193,53 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { circuitState should containTree { case MultiInfo(`expectedInfos`) => true } } + "source locators for basic register updates" should "be propagated to Verilog" in { + val result = compileBody(s""" + |input clock : Clock + |input reset : UInt<1> + |output io : { flip in : UInt<8>, out : UInt<8>} + |reg r : UInt<8>, clock + |r <= io.in $Info1 + |io.out <= r + |""".stripMargin + ) + result should containLine (s"r <= io_in; //$Info1") + } + + "source locators for register reset" should "be propagated to Verilog" in { + val result = compileBody(s""" + |input clock : Clock + |input reset : UInt<1> + |output io : { flip in : UInt<8>, out : UInt<8>} + |reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h0"))) $Info3 + |r <= io.in $Info1 + |io.out <= r + |""".stripMargin + ) + result should containLine (s"if (reset) begin //$Info3") + result should containLine (s"r <= 8'h0; //$Info3") + result should containLine (s"r <= io_in; //$Info1") + } + + "source locators for complex register updates" should "be propagated to Verilog" in { + val result = compileBody(s""" + |input clock : Clock + |input reset : UInt<1> + |output io : { flip in : UInt<8>, flip a : UInt<1>, out : UInt<8>} + |reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h0"))) $Info1 + |r <= UInt<2>(2) $Info2 + |when io.a : $Info3 + | r <= io.in $Info4 + |io.out <= r + |""".stripMargin + ) + result should containLine (s"if (reset) begin //$Info1") + result should containLine (s"r <= 8'h0; //$Info1") + result should containLine (s"end else if (io_a) begin //$Info3") + result should containLine (s"r <= io_in; //$Info4") + result should containLine (s"r <= 8'h2; //$Info2") + } + "FileInfo" should "be able to contain a escaped characters" in { def input(info: String): String = s"""circuit m: @[$info] |