diff options
Diffstat (limited to 'src/test')
8 files changed, 30 insertions, 33 deletions
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala index e0ed6fdb..42ba031a 100644 --- a/src/test/scala/firrtlTests/CustomTransformSpec.scala +++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala @@ -79,7 +79,7 @@ class CustomTransformSpec extends FirrtlFlatSpec { def inputForm = HighForm def outputForm = HighForm def execute(s: CircuitState) = { - println(name) + assert(name.endsWith("A")) s } } diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index b4f61dfd..4df711b3 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -76,21 +76,21 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities val optionsManager = new ExecutionOptionsManager("test") optionsManager.parse(Array("--top-name", "dog", "fox", "tardigrade", "stomatopod")) should be(true) - println(s"programArgs ${optionsManager.commonOptions.programArgs}") + info(s"programArgs ${optionsManager.commonOptions.programArgs}") optionsManager.commonOptions.programArgs.length should be(3) optionsManager.commonOptions.programArgs should be("fox" :: "tardigrade" :: "stomatopod" :: Nil) optionsManager.commonOptions = CommonOptions() optionsManager.parse( Array("dog", "stomatopod")) should be(true) - println(s"programArgs ${optionsManager.commonOptions.programArgs}") + info(s"programArgs ${optionsManager.commonOptions.programArgs}") optionsManager.commonOptions.programArgs.length should be(2) optionsManager.commonOptions.programArgs should be("dog" :: "stomatopod" :: Nil) optionsManager.commonOptions = CommonOptions() optionsManager.parse( Array("fox", "--top-name", "dog", "tardigrade", "stomatopod")) should be(true) - println(s"programArgs ${optionsManager.commonOptions.programArgs}") + info(s"programArgs ${optionsManager.commonOptions.programArgs}") optionsManager.commonOptions.programArgs.length should be(3) optionsManager.commonOptions.programArgs should be("fox" :: "tardigrade" :: "stomatopod" :: Nil) @@ -498,13 +498,12 @@ class VcdSuppressionSpec extends FirrtlFlatSpec { val harness = new File(testDir, s"top.cpp") copyResourceToFile(cppHarnessResourceName, harness) - verilogToCpp(prefix, testDir, Seq.empty, harness, suppress).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, Seq.empty, harness, suppress) #&& + cppToExe(prefix, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(prefix, testDir)) val vcdFile = new File(s"$testDir/dump.vcd") - println(s"file ${vcdFile.getAbsolutePath} ${vcdFile.exists()}") vcdFile.exists() should be(! suppress) } diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index 1ff5b72f..b0d750d2 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -7,18 +7,17 @@ import java.security.Permission import logger.LazyLogging -import scala.sys.process._ import org.scalatest._ import org.scalatest.prop._ import firrtl._ import firrtl.ir._ -import firrtl.Parser.{IgnoreInfo, UseInfo} -import firrtl.analyses.{GetNamespace, InstanceGraph, ModuleNamespaceAnnotation} +import firrtl.Parser.UseInfo +import firrtl.stage.{FirrtlFileAnnotation, InfoModeAnnotation, RunFirrtlTransformAnnotation} +import firrtl.analyses.{GetNamespace, ModuleNamespaceAnnotation} import firrtl.annotations._ import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules} import firrtl.util.BackendCompilationUtilities -import scala.collection.mutable class CheckLowForm extends SeqTransform { def inputForm = LowForm @@ -109,16 +108,17 @@ trait FirrtlRunners extends BackendCompilationUtilities { customTransforms: Seq[Transform] = Seq.empty, annotations: AnnotationSeq = Seq.empty): File = { val testDir = createTestDirectory(prefix) - copyResourceToFile(s"${srcDir}/${prefix}.fir", new File(testDir, s"${prefix}.fir")) - - val optionsManager = new ExecutionOptionsManager(prefix) with HasFirrtlOptions { - commonOptions = CommonOptions(topName = prefix, targetDirName = testDir.getPath) - firrtlOptions = FirrtlExecutionOptions( - infoModeName = "ignore", - customTransforms = customTransforms ++ extraCheckTransforms, - annotations = annotations.toList) - } - firrtl.Driver.execute(optionsManager) + val inputFile = new File(testDir, s"${prefix}.fir") + copyResourceToFile(s"${srcDir}/${prefix}.fir", inputFile) + + val annos = + FirrtlFileAnnotation(inputFile.toString) +: + TargetDirAnnotation(testDir.toString) +: + InfoModeAnnotation("ignore") +: + annotations ++: + (customTransforms ++ extraCheckTransforms).map(RunFirrtlTransformAnnotation(_)) + + (new firrtl.stage.FirrtlStage).run(annos) testDir } @@ -146,8 +146,9 @@ trait FirrtlRunners extends BackendCompilationUtilities { file } - verilogToCpp(prefix, testDir, verilogFiles, harness).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, verilogFiles, harness) #&& + cppToExe(prefix, testDir) ! + loggingProcessLogger assert(executeExpectingSuccess(prefix, testDir)) } } diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index b7fd0084..732cd501 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -42,8 +42,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec { copyResourceToFile(cppHarnessResourceName, harness) // topFile will be compiled by Verilator command by default but we need to also include dutFile - verilogToCpp(top, testDir, Seq(dutFile), harness).! - cppToExe(top, testDir).! + verilogToCpp(top, testDir, Seq(dutFile), harness) #&& + cppToExe(top, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(top, testDir)) } } diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala index 3241db16..2da10b7f 100644 --- a/src/test/scala/firrtlTests/RenameMapSpec.scala +++ b/src/test/scala/firrtlTests/RenameMapSpec.scala @@ -161,7 +161,6 @@ class RenameMapSpec extends FirrtlFlatSpec { t.instOf("a", "A" + idx) }.ref("ref") val (millis, rename) = firrtl.Utils.time(renames.get(deepTarget)) - println(s"${(deepTarget.tokens.size - 1) / 2} -> $millis") //rename should be(None) } } @@ -281,7 +280,7 @@ class RenameMapSpec extends FirrtlFlatSpec { renames.record(top.module("E").instOf("f", "F"), top.module("E").ref("g")) a [IllegalRenameException] shouldBe thrownBy { - println(renames.get(top.module("E").instOf("f", "F").ref("g"))) + renames.get(top.module("E").instOf("f", "F").ref("g")) } } diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 208d9e6c..aaf2a584 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -23,8 +23,8 @@ class PrintfSpec extends FirrtlPropSpec { val harness = new File(testDir, s"top.cpp") copyResourceToFile(cppHarnessResourceName, harness) - verilogToCpp(prefix, testDir, Seq(), harness).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, Seq(), harness) #&& + cppToExe(prefix, testDir) ! loggingProcessLogger // Check for correct Printf: // Count up from 0, match decimal, hex, and binary diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala index da154b6a..1bc4c927 100644 --- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala @@ -9,7 +9,6 @@ import firrtlTests.FirrtlPropSpec class TargetSpec extends FirrtlPropSpec { def check(comp: Target): Unit = { val named = Target.convertTarget2Named(comp) - println(named) val comp2 = Target.convertNamed2Target(named) assert(comp.toGenericTarget.complete == comp2) } @@ -43,7 +42,6 @@ class TargetSpec extends FirrtlPropSpec { val x_reg0_data = top.instOf("x", "X").ref("reg0").field("data") top.instOf("x", "x") top.ref("y") - println(x_reg0_data) } property("Should serialize and deserialize") { val circuit = CircuitTarget("Circuit") diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index 17eecc65..060554c0 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -25,8 +25,8 @@ trait VerilogExecution extends TestExecution { copyResourceToFile(cppHarnessResourceName, harness) // Make and run Verilog simulation - verilogToCpp(c.main, testDir, Nil, harness).! - cppToExe(c.main, testDir).! + verilogToCpp(c.main, testDir, Nil, harness) #&& + cppToExe(c.main, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(c.main, testDir)) } } |