1 files changed, 21 insertions, 14 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index db1b6236..ae06c331 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -739,8 +739,8 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
     val annos = Seq(
-      DescriptionAnnotation(ComponentName("a", modName), "multi\nline"),
-      DescriptionAnnotation(ComponentName("b", modName), "single line"))
+      DocStringAnnotation(ComponentName("a", modName), "multi\nline"),
+      DocStringAnnotation(ComponentName("b", modName), "single line"))
     val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos), Seq.empty)
     val output = finalState.getEmittedCircuit.value
     for (c <- check) {
@@ -782,9 +782,9 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
     val annos = Seq(
-      DescriptionAnnotation(ComponentName("d", modName), "multi\nline"),
-      DescriptionAnnotation(ComponentName("e", modName), "multi\nline"),
-      DescriptionAnnotation(ComponentName("f", modName), "single line"))
+      DocStringAnnotation(ComponentName("d", modName), "multi\nline"),
+      DocStringAnnotation(ComponentName("e", modName), "multi\nline"),
+      DocStringAnnotation(ComponentName("f", modName), "single line"))
     val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos), Seq.empty)
     val output = finalState.getEmittedCircuit.value
     for (c <- check) {
@@ -819,7 +819,7 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
     )
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
-    val annos = Seq(DescriptionAnnotation(modName, "multi\nline"))
+    val annos = Seq(DocStringAnnotation(modName, "multi\nline"))
     val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos), Seq.empty)
     val output = finalState.getEmittedCircuit.value
     for (c <- check) {
@@ -846,29 +846,36 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
         | *
         | * line2
         | */
-        |module Test(""".stripMargin,
+        |(* parallel_case *)
+        |module Test(
+        |""".stripMargin,
       """  /* line3
         |   *
         |   * line4
         |   */
+        |  (* full_case *)
         |  input   a,""".stripMargin,
       """  /* line5
         |   *
         |   * line6
         |   */
+        |  (* parallel_case, mark_debug *)
         |  wire  d = """.stripMargin
     )
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
     val annos = Seq(
-      DescriptionAnnotation(modName, "line1"),
-      DescriptionAnnotation(modName, "line2"),
-      DescriptionAnnotation(ComponentName("a", modName), "line3"),
-      DescriptionAnnotation(ComponentName("a", modName), "line4"),
-      DescriptionAnnotation(ComponentName("d", modName), "line5"),
-      DescriptionAnnotation(ComponentName("d", modName), "line6")
+      DocStringAnnotation(modName, "line1"),
+      DocStringAnnotation(modName, "line2"),
+      AttributeAnnotation(modName, "parallel_case"),
+      DocStringAnnotation(ComponentName("a", modName), "line3"),
+      DocStringAnnotation(ComponentName("a", modName), "line4"),
+      AttributeAnnotation(ComponentName("a", modName), "full_case"),
+      DocStringAnnotation(ComponentName("d", modName), "line5"),
+      DocStringAnnotation(ComponentName("d", modName), "line6"),
+      AttributeAnnotation(ComponentName("d", modName), "parallel_case"),
+      AttributeAnnotation(ComponentName("d", modName), "mark_debug")
     )
-    val writer = new java.io.StringWriter
     val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos), Seq.empty)
     val output = finalState.getEmittedCircuit.value
     for (c <- check) {