diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/InlineAcrossCastsSpec.scala (renamed from src/test/scala/firrtlTests/InlineCastsSpec.scala) | 6 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/InlineCastsSpec.scala b/src/test/scala/firrtlTests/InlineAcrossCastsSpec.scala index 7a248def..669ae077 100644 --- a/src/test/scala/firrtlTests/InlineCastsSpec.scala +++ b/src/test/scala/firrtlTests/InlineAcrossCastsSpec.scala @@ -2,11 +2,11 @@ package firrtlTests -import firrtl.transforms.InlineCastsTransform +import firrtl.transforms.InlineAcrossCastsTransform import firrtl.testutils.FirrtlFlatSpec import firrtl.testutils.FirrtlCheckers._ -class InlineCastsEquivalenceSpec extends FirrtlFlatSpec { +class InlineAcrossCastsEquivalenceSpec extends FirrtlFlatSpec { /* * Note: InlineCasts is still part of mverilog, so this test must both: * - Test that the InlineCasts fix is effective given the current mverilog @@ -25,7 +25,7 @@ class InlineCastsEquivalenceSpec extends FirrtlFlatSpec { | output o: SInt<8> | o <= pad(asSInt(UInt<2>("h1")), 8) |""".stripMargin - firrtlEquivalenceTest(input, Seq(new InlineCastsTransform)) + firrtlEquivalenceTest(input, Seq(new InlineAcrossCastsTransform)) } it should "not inline complex expressions into other complex expressions" in { diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index bdc72e7b..d56ca657 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -247,7 +247,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.ReplaceTruncatingArithmetic, new firrtl.transforms.InlineBitExtractionsTransform, new firrtl.transforms.PropagatePresetAnnotations, - new firrtl.transforms.InlineCastsTransform, + new firrtl.transforms.InlineAcrossCastsTransform, new firrtl.transforms.LegalizeClocksTransform, new firrtl.transforms.FlattenRegUpdate, firrtl.passes.VerilogModulusCleanup, @@ -271,7 +271,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.ReplaceTruncatingArithmetic, new firrtl.transforms.InlineBitExtractionsTransform, new firrtl.transforms.PropagatePresetAnnotations, - new firrtl.transforms.InlineCastsTransform, + new firrtl.transforms.InlineAcrossCastsTransform, new firrtl.transforms.LegalizeClocksTransform, new firrtl.transforms.FlattenRegUpdate, new firrtl.transforms.DeadCodeElimination, |