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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/CompilerTests.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index 8ec7665c..a9fce0c2 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -93,8 +93,6 @@ circuit Top : " b <= _GEN_0\n\n" ).reduce(_ + "\n" + _) "A circuit" should "match exactly to its MidForm state" in { - val parsedOutput = parse(getOutput) - val checkedOutput = parse(check) (parse(getOutput)) should be (parse(check)) } } |