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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/LowerTypesSpec.scala | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala index 9e58b74c..da84b362 100644 --- a/src/test/scala/firrtlTests/LowerTypesSpec.scala +++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala @@ -456,6 +456,23 @@ class LowerTypesUniquifySpec extends FirrtlFlatSpec { executeTest(input, expected) } + it should "remove index express in SubAccess" in { + val input = + s"""circuit Bug : + | module Bug : + | input in0 : UInt<1> [2][2] + | input in1 : UInt<1> [2] + | input in2 : UInt<1> [2] + | output out : UInt<1> + | out <= in0[in1[in2[0]]][in1[in2[1]]] + |""".stripMargin + val expected = Seq( + "out <= _in0_in1_in1_in2_1" + ) + + executeTest(input, expected) + } + it should "rename memories" in { val input = """circuit Test : |