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-rw-r--r--src/test/resources/blackboxes/LargeParam.v7
-rw-r--r--src/test/resources/blackboxes/LargeParamTester.fir7
-rw-r--r--src/test/scala/firrtlTests/CheckSpec.scala136
-rw-r--r--src/test/scala/firrtlTests/transforms/DedupTests.scala9
4 files changed, 149 insertions, 10 deletions
diff --git a/src/test/resources/blackboxes/LargeParam.v b/src/test/resources/blackboxes/LargeParam.v
index 84e1a1cf..3a0dcd9e 100644
--- a/src/test/resources/blackboxes/LargeParam.v
+++ b/src/test/resources/blackboxes/LargeParam.v
@@ -1,7 +1,12 @@
// See LICENSE for license details.
-module LargeParam #(parameter DATA=0, WIDTH=1) (
+module LargeParamUnsigned #(parameter DATA=0, WIDTH=1) (
output [WIDTH-1:0] out
);
assign out = DATA;
endmodule
+module LargeParamSigned #(parameter DATA=0, WIDTH=1) (
+ output signed [WIDTH-1:0] out
+);
+ assign out = DATA;
+endmodule
diff --git a/src/test/resources/blackboxes/LargeParamTester.fir b/src/test/resources/blackboxes/LargeParamTester.fir
index bb0ebdf5..29027c36 100644
--- a/src/test/resources/blackboxes/LargeParamTester.fir
+++ b/src/test/resources/blackboxes/LargeParamTester.fir
@@ -3,21 +3,21 @@ circuit LargeParamTester :
extmodule LargeParam :
output out : UInt<1>
- defname = LargeParam
+ defname = LargeParamUnsigned
parameter WIDTH = 1
parameter DATA = 0
extmodule LargeParam_1 :
output out : UInt<128>
- defname = LargeParam
+ defname = LargeParamUnsigned
parameter WIDTH = 128
parameter DATA = 9223372036854775807000
extmodule LargeParam_2 :
output out : SInt<128>
- defname = LargeParam
+ defname = LargeParamSigned
parameter WIDTH = 128
parameter DATA = -9223372036854775807000
@@ -40,4 +40,3 @@ circuit LargeParamTester :
printf(clock, UInt(1), "Assertion failed\nTest Failed!\n")
stop(clock, UInt(1), 1)
stop(clock, UInt(1), 0)
-
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index b49054ad..5c38bf30 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -399,6 +399,142 @@ class CheckSpec extends AnyFlatSpec with Matchers {
checkHighInput(input)
}
}
+
+ behavior of "CheckHighForm running on circuits containing ExtModules"
+
+ it should "throw an exception if parameterless ExtModules have the same ports, but different widths" in {
+ val input =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input a: UInt<1>
+ | defname = bar
+ | extmodule Baz:
+ | input a: UInt<2>
+ | defname = bar
+ | module Foo:
+ | skip
+ |""".stripMargin
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input)
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ }
+
+ it should "throw an exception if ExtModules have different port names, but identical widths" in {
+ val input =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input a: UInt<1>
+ | defname = bar
+ | extmodule Baz:
+ | input b: UInt<1>
+ | defname = bar
+ | module Foo:
+ | skip
+ |""".stripMargin
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input)
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ }
+
+ it should "NOT throw an exception if ExtModules have parameters, matching port names, but different widths" in {
+ val input =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input a: UInt<1>
+ | defname = bar
+ | parameter width = 1
+ | extmodule Baz:
+ | input a: UInt<2>
+ | defname = bar
+ | parameter width = 2
+ | module Foo:
+ | skip
+ |""".stripMargin
+ checkHighInput(input)
+ }
+
+ it should "throw an exception if ExtModules have matching port names and widths, but a different order" in {
+ val input =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input a: UInt<1>
+ | input b: UInt<1>
+ | defname = bar
+ | extmodule Baz:
+ | input b: UInt<1>
+ | input a: UInt<1>
+ | defname = bar
+ | module Foo:
+ | skip
+ |""".stripMargin
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input)
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ }
+
+ it should "throw an exception if ExtModules have matching port names, but one is a Clock and one is a UInt<1>" in {
+ val input =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input a: UInt<1>
+ | defname = bar
+ | extmodule Baz:
+ | input a: Clock
+ | defname = bar
+ | module Foo:
+ | skip
+ |""".stripMargin
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input)
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ }
+
+ it should "throw an exception if ExtModules have differing concrete reset types" in {
+ def input(rst1: String, rst2: String) =
+ s"""|circuit Foo:
+ | extmodule Bar:
+ | input rst: $rst1
+ | defname = bar
+ | extmodule Baz:
+ | input rst: $rst2
+ | defname = bar
+ | module Foo:
+ | skip
+ |""".stripMargin
+ info("exception thrown for 'UInt<1>' compared to 'AsyncReset'")
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input("UInt<1>", "AsyncReset"))
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ info("exception thrown for 'UInt<1>' compared to 'Reset'")
+ assertThrows[CheckHighForm.DefnameDifferentPortsException] {
+ try {
+ checkHighInput(input("UInt<1>", "Reset"))
+ } catch {
+ case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+ }
+ }
+ }
+
}
object CheckSpec {
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 5776db31..8ab3026c 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -193,13 +193,13 @@ class DedupModuleTests extends HighTransformSpec {
| module A_ : @[xx 1:1]
| output y: UInt<1> @[xx 1:1]
| inst c of C
- | y <= c.v
+ | y <= c.u
| extmodule B : @[aa 3:3]
| output u : UInt<1> @[aa 4:4]
| defname = BB
| parameter N = 0
| extmodule C : @[bb 5:5]
- | output v : UInt<1> @[bb 6:6]
+ | output u : UInt<1> @[bb 6:6]
| defname = BB
| parameter N = 0
""".stripMargin
@@ -238,13 +238,13 @@ class DedupModuleTests extends HighTransformSpec {
| module A_ : @[xx 1:1]
| output y: UInt<1> @[xx 1:1]
| inst c of C
- | y <= c.v
+ | y <= c.u
| extmodule B : @[aa 3:3]
| output u : UInt<1> @[aa 4:4]
| defname = ${defnames._1}
| parameter N = ${params._1}
| extmodule C : @[bb 5:5]
- | output v : UInt<1> @[bb 6:6]
+ | output u : UInt<1> @[bb 6:6]
| defname = ${defnames._2}
| parameter N = ${params._2}
""".stripMargin
@@ -875,4 +875,3 @@ class DedupModuleTests extends HighTransformSpec {
csDeduped.annotations.toSeq should contain (expectedAnnB)
}
}
-
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:58:40 +0000