1 files changed, 11 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index eb404393..1cee9f74 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -635,6 +635,17 @@ class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
     outputState.circuit.serialize should include("output bar_foo")
     outputState.annotations.toSeq should be(empty)
   }
+
+  "Unnamed side-affecting statements" should s"not be included as potential sources" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clock : Clock
+        |    printf(clock, UInt<1>(1), "")
+        |    stop(clock, UInt<1>(1), 1)
+        |""".stripMargin
+    execute(input, input, Seq())
+  }
 }
 
 class AggregateTopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {