1 files changed, 16 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index e40a770b..06e5dccd 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -182,4 +182,20 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     // Check declaration before use is maintained
     passes.CheckHighForm.execute(result)
   }
+
+  it should "order registers respecting initializations" in {
+    val result = compileBody(
+      s"""|input clock : Clock
+          |input foo : UInt<2>
+          |output bar : UInt<2>
+          |wire y_fault : UInt<2>
+          |reg y : UInt<2>, clock with :
+          |  reset => (UInt<1>("h0"), y_fault)
+          |y_fault <= foo
+          |bar <= y
+          |""".stripMargin)
+    // Check declaration before use is maintained
+    passes.CheckHighForm.execute(result)
+  }
+
 }