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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 28c1d823..60cf1b8b 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1638,6 +1638,20 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec { firrtlEquivalenceTest(input, transforms) } + // https://github.com/chipsalliance/firrtl/issues/2034 + "SInt OR with constant zero" should "have the correct widths" in { + val input = + s"""circuit WidthsOrSInt : + | module WidthsOrSInt : + | input in : SInt<1> + | input in2 : SInt<4> + | output out : UInt<8> + | output out2 : UInt<8> + | out <= or(in, SInt<8>(0)) + | out2 <= or(in2, SInt<8>(0))""".stripMargin + firrtlEquivalenceTest(input, transforms) + } + "addition by zero width wires" should "have the correct widths" in { val input = s"""circuit ZeroWidthAdd: |