diff options
Diffstat (limited to 'src/test')
3 files changed, 80 insertions, 27 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 6ab54159..cc6377ee 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1528,6 +1528,41 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec { execute(input, check, Seq.empty) } + "ConstProp" should "compose with Dedup and not duplicate modules " in { + val input = + """circuit Top : + | module child : + | input x : UInt<1> + | output z : UInt<1> + | z <= not(x) + | module child_1 : + | input x : UInt<1> + | output z : UInt<1> + | z <= not(x) + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst c of child + | inst c_1 of child_1 + | c.x <= x + | c_1.x <= x + | z <= and(c.z, c_1.z)""".stripMargin + val check = + """circuit Top : + | module child : + | input x : UInt<1> + | output z : UInt<1> + | z <= not(x) + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst c of child + | inst c_1 of child + | z <= and(c.z, c_1.z) + | c.x <= x + | c_1.x <= x""".stripMargin + execute(input, check, Seq(dontTouch("child.z"), dontTouch("child_1.z"))) + } } class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index a9084f0b..f1c0001a 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -491,6 +491,42 @@ class DCETests extends FirrtlFlatSpec { (verilog shouldNot include).regex("""fwrite""") (verilog shouldNot include).regex("""fatal""") } + + "DCE" should "not duplicate unnecessarily" in { + val input = + """circuit Top : + | module child : + | input x : UInt<1> + | output z : UInt<1> + | z <= not(x) + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst c of child + | inst c_1 of child + | c.x <= x + | c_1.x <= x + | z <= and(c.z, c_1.z)""".stripMargin + val check = + """circuit Top : + | module child : + | input x : UInt<1> + | output z : UInt<1> + | z <= not(x) + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst c of child + | inst c_1 of child + | z <= and(c.z, c_1.z) + | c.x <= x + | c_1.x <= x""".stripMargin + val top = CircuitTarget("Top").module("Top") + val annos = + Seq(top.instOf("c", "child").ref("z"), top.instOf("c_1", "child").ref("z")) + .map(DontTouchAnnotation(_)) + exec(input, check, annos) + } } class DCECommandLineSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala index bb833f0b..56079c31 100644 --- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala @@ -121,55 +121,37 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { val outputState = new LowFirrtlCompiler().compile(inputState, customTransforms) val check = """circuit Top : - | module Leaf___Top_m1_l1 : - | input i : UInt<1> - | output o : UInt<1> - | - | node a = i - | o <= i - | | module Leaf : | input i : UInt<1> | output o : UInt<1> - | - | skip + + | node a = i | o <= i | - | module Middle___Top_m1 : - | input i : UInt<1> - | output o : UInt<1> - | - | inst l1 of Leaf___Top_m1_l1 - | inst l2 of Leaf - | o <= l2.o - | l1.i <= i - | l2.i <= l1.o - | | module Middle : | input i : UInt<1> | output o : UInt<1> - | + | inst l1 of Leaf | inst l2 of Leaf | o <= l2.o | l1.i <= i | l2.i <= l1.o - | + | module Top : | input i : UInt<1> | output o : UInt<1> - | - | inst m1 of Middle___Top_m1 + + | inst m1 of Middle | inst m2 of Middle | o <= m2.o | m1.i <= i - | m2.i <= m1.o - | - """.stripMargin + | m2.i <= m1.o""".stripMargin + canonicalize(outputState.circuit).serialize should be(canonicalize(parse(check)).serialize) outputState.annotations.collect { case x: DontTouchAnnotation => x.target - } should be(Seq(Top.circuitTarget.module("Leaf___Top_m1_l1").ref("a"))) + } should be(Seq(Top.circuitTarget.module("Top").instOf("m1", "Middle").instOf("l1", "Leaf").ref("a"))) } property("No name conflicts between old and new modules") { |