diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UtilsSpec.scala | 170 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala | 57 |
2 files changed, 227 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/UtilsSpec.scala b/src/test/scala/firrtlTests/UtilsSpec.scala index 99f1ffd0..1048b370 100644 --- a/src/test/scala/firrtlTests/UtilsSpec.scala +++ b/src/test/scala/firrtlTests/UtilsSpec.scala @@ -46,4 +46,174 @@ class UtilsSpec extends AnyFlatSpec { (Utils.expandRef(wr)) should be(expected) } + + def combineTest(circuits: Seq[String], expected: String) = { + (Utils.orderAgnosticEquality(Utils.combine(circuits.map(c => Parser.parse(c))), Parser.parse(expected))) should be( + true + ) + } + + "combine" should "merge multiple module circuits" in { + val input = Seq( + """|circuit Top: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | extmodule Child1: + | output foo: UInt<32> + | defname = Child1 + | + | extmodule Child2: + | output foo: UInt<32> + | defname = Child2 + | + | module Top: + | output foo: UInt<32> + | inst c1 of Child1 + | inst c2 of Child2 + | inst e of External + | foo <= tail(add(add(c1.foo, c2.bar), e.foo), 1) + |""".stripMargin, + """|circuit Child1: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Child1: + | output foo: UInt<32> + | inst e of External + | foo <= e.foo + |""".stripMargin, + """|circuit Child2: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Child2: + | output bar: UInt<32> + | inst e of External + | bar <= e.foo + |""".stripMargin + ) + + val output = + """|circuit Top: + | module Top: + | output foo: UInt<32> + | inst c1 of Child1 + | inst c2 of Child2 + | inst e of External + | foo <= tail(add(add(c1.foo, c2.bar), e.foo), 1) + | + | module Child1: + | output foo: UInt<32> + | inst e of External + | foo <= e.foo + | + | module Child2: + | output bar: UInt<32> + | inst e of External + | bar <= e.foo + | + | extmodule External: + | output foo: UInt<32> + | defname = External + |""".stripMargin + + combineTest(input, output) + } + + "combine" should "dedup ExtModules if an implementation exists" in { + val input = Seq( + """|circuit Top: + | extmodule Child: + | output foo: UInt<32> + | defname = Child + | + | module Top: + | output foo: UInt<32> + | inst c of Child + | foo <= c.foo + |""".stripMargin, + """|circuit Child: + | module Child: + | output foo: UInt<32> + | + | skip + |""".stripMargin + ) + + val output = + """|circuit Top: + | module Top: + | output foo: UInt<32> + | inst c of Child + | foo <= c.foo + | + | module Child: + | output foo: UInt<32> + | + | skip + |""".stripMargin + + combineTest(input, output) + } + + "combine" should "support lone ExtModules" in { + val input = Seq( + """|circuit Top: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Top: + | output foo: UInt<32> + | inst e of External + | foo <= e.foo + |""".stripMargin + ) + + val output = + """|circuit Top: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Top: + | output foo: UInt<32> + | inst e of External + | foo <= e.foo + |""".stripMargin + + combineTest(input, output) + } + + "combine" should "fail with multiple lone Modules" in { + val input = Seq( + """|circuit Top: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Top: + | output foo: UInt<32> + | inst e of External + | foo <= e.foo + |""".stripMargin, + """|circuit Top2: + | extmodule External: + | output foo: UInt<32> + | defname = External + | + | module Top2: + | output bar: UInt<32> + | inst e of External + | bar <= e.foo + |""".stripMargin + ) + + a[java.lang.AssertionError] shouldBe thrownBy { combineTest(input, "") } + } + } diff --git a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala index d51fc164..30e03b3c 100644 --- a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala +++ b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala @@ -246,6 +246,16 @@ class FirrtlMainSpec args = Array("-X", "sverilog", "-e", "sverilog"), files = Seq("Top.sv", "Child.sv") ), + /* Test all one protobuf per module emitters */ + FirrtlMainTest( + args = Array("-X", "none", "--emit-modules-protobuf", "chirrtl"), + files = Seq("Top.pb", "Child.pb") + ), + FirrtlMainTest(args = Array("-X", "none", "-p", "mhigh"), files = Seq("Top.mhi.pb", "Child.mhi.pb")), + FirrtlMainTest(args = Array("-X", "none", "-p", "high"), files = Seq("Top.hi.pb", "Child.hi.pb")), + FirrtlMainTest(args = Array("-X", "none", "-p", "middle"), files = Seq("Top.mid.pb", "Child.mid.pb")), + FirrtlMainTest(args = Array("-X", "none", "-p", "low"), files = Seq("Top.lo.pb", "Child.lo.pb")), + FirrtlMainTest(args = Array("-X", "none", "-p", "low-opt"), files = Seq("Top.lo.pb", "Child.lo.pb")), /* Test mixing of -E with -e */ FirrtlMainTest( args = Array("-X", "middle", "-E", "high", "-e", "middle"), @@ -324,6 +334,47 @@ class FirrtlMainSpec new File(td.buildDir + "/Foo.hi.fir") should (exist) } + Scenario("User compiles to multiple Protocol Buffers") { + val f = new FirrtlMainFixture + val td = new TargetDirectoryFixture("multi-protobuf") + val c = new SimpleFirrtlCircuitFixture + val protobufs = Seq("Top.pb", "Child.pb") + + And("some input multi-module FIRRTL IR") + val inputFile: Array[String] = { + val in = new File(td.dir, c.main) + val pw = new PrintWriter(in) + pw.write(c.input) + pw.close() + Array("-i", in.toString) + } + + When("the user tries to emit a circuit to multiple Protocol Buffer files in the target directory") + f.stage.main( + inputFile ++ Array("-X", "none", "-p", "chirrtl", "-td", td.buildDir.toString) + ) + + protobufs.foreach { f => + Then(s"file '$f' should be emitted") + val out = new File(td.buildDir + s"/$f") + out should (exist) + } + + When("the user compiles the Protobufs to a single FIRRTL IR") + f.stage.main( + Array("-I", td.buildDir.toString, "-X", "none", "-E", "chirrtl", "-td", td.buildDir.toString, "-o", "Foo") + ) + + Then("one single FIRRTL file should be emitted") + val outFile = new File(td.buildDir + "/Foo.fir") + outFile should (exist) + And("it should be the same as using FIRRTL input") + firrtl.Utils.orderAgnosticEquality( + firrtl.Parser.parse(c.input), + firrtl.Parser.parseFile(td.buildDir + "/Foo.fir", firrtl.Parser.IgnoreInfo) + ) should be(true) + } + } info("As a FIRRTL command line user") @@ -381,6 +432,12 @@ class FirrtlMainSpec circuit = None, stdout = Some("Unknown compiler name 'Verilog'! (Did you misspell it?)"), result = 1 + ), + FirrtlMainTest( + args = Array("-I", "test_run_dir/I-DO-NOT-EXIST"), + circuit = None, + stdout = Some("Directory 'test_run_dir/I-DO-NOT-EXIST' not found!"), + result = 1 ) ) .foreach(runStageExpectFiles) |