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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 7feb4a00..245c32e8 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -290,4 +290,25 @@ class UnitTests extends FirrtlFlatSpec { } } } + + "Partial connecting incompatable types" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + CheckTypes) + val input = + """circuit Unit : + | module Unit : + | input foo : { bar : UInt<32> } + | output bar : UInt<32> + | bar <- foo + |""".stripMargin + intercept[PassException] { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + + } } |
