2 files changed, 4 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala
index 95c2ee93..4161d29b 100644
--- a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala
+++ b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala
@@ -38,7 +38,6 @@ class FirrtlOptionsViewSpec extends AnyFlatSpec with Matchers {
     val out = view[FirrtlOptions](annotations)
 
     out.outputFileName should be (Some("bar"))
-    out.compiler.getClass should be (classOf[BazCompiler])
     out.infoModeName should be ("use")
     out.firrtlCircuit should be (Some(grault))
   }
@@ -59,7 +58,6 @@ class FirrtlOptionsViewSpec extends AnyFlatSpec with Matchers {
     val out = view[FirrtlOptions](annotations ++ overwrites)
 
     out.outputFileName should be (Some("bar_"))
-    out.compiler.getClass should be (classOf[Baz_Compiler])
     out.infoModeName should be ("gen")
     out.firrtlCircuit should be (Some(grault_))
   }
diff --git a/src/test/scala/firrtlTests/stage/phases/AddDefaultsSpec.scala b/src/test/scala/firrtlTests/stage/phases/AddDefaultsSpec.scala
index 89f5193c..b600e6c5 100644
--- a/src/test/scala/firrtlTests/stage/phases/AddDefaultsSpec.scala
+++ b/src/test/scala/firrtlTests/stage/phases/AddDefaultsSpec.scala
@@ -7,8 +7,8 @@ import firrtl.NoneCompiler
 import firrtl.annotations.Annotation
 import firrtl.stage.phases.AddDefaults
 import firrtl.transforms.BlackBoxTargetDirAnno
-import firrtl.stage.{CompilerAnnotation, InfoModeAnnotation}
-import firrtl.options.{Phase, TargetDirAnnotation}
+import firrtl.stage.{CompilerAnnotation, InfoModeAnnotation, RunFirrtlTransformAnnotation}
+import firrtl.options.{Dependency, Phase, TargetDirAnnotation}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
@@ -21,7 +21,8 @@ class AddDefaultsSpec extends AnyFlatSpec with Matchers {
   it should "add expected default annotations and nothing else" in new Fixture {
     val expected = Seq(
       (a: Annotation) => a match { case BlackBoxTargetDirAnno(b) => b == TargetDirAnnotation().directory },
-      (a: Annotation) => a match { case CompilerAnnotation(b) => b.getClass == CompilerAnnotation().compiler.getClass },
+      (a: Annotation) => a match { case RunFirrtlTransformAnnotation(e: firrtl.Emitter) =>
+        Dependency.fromTransform(e) == Dependency[firrtl.VerilogEmitter] },
       (a: Annotation) => a match { case InfoModeAnnotation(b) => b == InfoModeAnnotation().modeName } )
 
     phase.transform(Seq.empty).zip(expected).map { case (x, f) => f(x) should be (true) }