diff options
Diffstat (limited to 'src/test/scala')
5 files changed, 89 insertions, 46 deletions
diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index ae1e08e7..d26aadf2 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -206,18 +206,35 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities } // Deprecated - "Annotations can be read implicitly from the name of the circuit" in { + "Annotations can be read implicitly from the name of the circuit" - { + val input = """|circuit foo : + | module foo : + | input x : UInt<8> + | output y : UInt<8> + | y <= x""".stripMargin val top = "foo" val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions { commonOptions = commonOptions.copy(topName = top) + firrtlOptions = firrtlOptions.copy(firrtlSource = Some(input)) } val annoFile = new File(optionsManager.commonOptions.targetDirName, top + ".anno") - copyResourceToFile("/annotations/SampleAnnotations.anno", annoFile) - optionsManager.firrtlOptions.annotations.length should be(0) - val annos = Driver.getAnnotations(optionsManager) - annos.length should be(12) // 9 from circuit plus 3 general purpose - annos.count(_.isInstanceOf[InlineAnnotation]) should be(9) - annoFile.delete() + "Using Driver.getAnnotations" in { + copyResourceToFile("/annotations/SampleAnnotations.anno", annoFile) + optionsManager.firrtlOptions.annotations.length should be(0) + val annos = Driver.getAnnotations(optionsManager) + annos.length should be(12) // 9 from circuit plus 3 general purpose + annos.count(_.isInstanceOf[InlineAnnotation]) should be(9) + annoFile.delete() + } + "Using Driver.execute" in { + copyResourceToFile("/annotations/SampleAnnotations.anno", annoFile) + Driver.execute(optionsManager) match { + case r: FirrtlExecutionSuccess => + val annos = r.circuitState.annotations + annos.count(_.isInstanceOf[InlineAnnotation]) should be(9) + } + annoFile.delete() + } } // Deprecated diff --git a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala index 8f157131..eb061d8f 100644 --- a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala @@ -5,7 +5,6 @@ package annotationTests import firrtlTests._ import firrtl._ -import firrtl.stage.TargetDirAnnotation /** Looks for [[TargetDirAnnotation]] */ class FindTargetDirTransform(expected: String) extends Transform { diff --git a/src/test/scala/firrtlTests/options/ShellSpec.scala b/src/test/scala/firrtlTests/options/ShellSpec.scala index d87a9a30..50000550 100644 --- a/src/test/scala/firrtlTests/options/ShellSpec.scala +++ b/src/test/scala/firrtlTests/options/ShellSpec.scala @@ -2,12 +2,24 @@ package firrtlTests.options -import org.scalatest._ +import org.scalatest.{FlatSpec, Matchers} +import firrtl.annotations.NoTargetAnnotation import firrtl.options.Shell class ShellSpec extends FlatSpec with Matchers { + case object A extends NoTargetAnnotation + case object B extends NoTargetAnnotation + case object C extends NoTargetAnnotation + case object D extends NoTargetAnnotation + case object E extends NoTargetAnnotation + + trait AlphabeticalCli { this: Shell => + parser.opt[Unit]('c', "c-option").unbounded().action( (x, c) => C +: c ) + parser.opt[Unit]('d', "d-option").unbounded().action( (x, c) => D +: c ) + parser.opt[Unit]('e', "e-option").unbounded().action( (x, c) => E +: c ) } + behavior of "Shell" it should "detect all registered libraries and transforms" in { @@ -19,4 +31,10 @@ class ShellSpec extends FlatSpec with Matchers { info("Found BarLibrary") shell.registeredLibraries.map(_.getClass.getName) should contain ("firrtlTests.options.BarLibrary") } + + it should "correctly order annotations and options" in { + val shell = new Shell("foo") with AlphabeticalCli + + shell.parse(Array("-c", "-d", "-e"), Seq(A, B)).toSeq should be (Seq(A, B, C, D, E)) + } } diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala index c54e02e3..b4c27875 100644 --- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala +++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala @@ -8,7 +8,7 @@ import firrtl.ir._ import FirrtlCheckers._ -class GroupComponentsSpec extends LowTransformSpec { +class GroupComponentsSpec extends MiddleTransformSpec { def transform = new GroupComponents() val top = "Top" def topComp(name: String): ComponentName = ComponentName(name, ModuleName(top, CircuitName(top))) @@ -71,15 +71,18 @@ class GroupComponentsSpec extends LowTransformSpec { | output out: UInt<16> | inst inst of Child | node n = UInt<16>("h0") - | inst.in_IN <= in - | node a = UInt<16>("h0") - | node b = a + | wire a : UInt<16> + | wire b : UInt<16> | out <= inst.w_OUT + | inst.in_IN <= in + | a <= UInt<16>("h0") + | b <= a | module Child : - | input in_IN : UInt<16> | output w_OUT : UInt<16> - | node w = in_IN + | input in_IN : UInt<16> + | wire w : UInt<16> | w_OUT <= w + | w <= in_IN """.stripMargin execute(input, check, groups) } diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala index 5a6b3420..d5b1aa6d 100644 --- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala +++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala @@ -55,7 +55,7 @@ trait TopWiringTestsCommon extends FirrtlRunners { /** * Tests TopWiring transformation */ -class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { +class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon { "The signal x in module C" should s"be connected to Top port with topwiring prefix and outputfile in $testDirName" in { val input = @@ -78,8 +78,8 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output x: UInt<1> | x <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"), TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)) val check = @@ -113,7 +113,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal x in module C inst c1 and c2" should + "The signal x in module C inst c1 and c2" should s"be connected to Top port with topwiring prefix and outfile in $testDirName" in { val input = """circuit Top : @@ -177,7 +177,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal x in module C" should + "The signal x in module C" should s"be connected to Top port with topwiring prefix and outputfile in $testDirName, after name colission" in { val input = """circuit Top : @@ -203,8 +203,8 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output x: UInt<1> | x <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"), TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)) val check = @@ -213,14 +213,16 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output topwiring_a1_b1_c1_x_0: UInt<1> | inst a1 of A | inst a2 of A_ - | node topwiring_a1_b1_c1_x = UInt<1>("h0") + | wire topwiring_a1_b1_c1_x : UInt<1> + | topwiring_a1_b1_c1_x <= UInt<1>("h0") | topwiring_a1_b1_c1_x_0 <= a1.topwiring_b1_c1_x_0 | module A : | output x: UInt<1> | output topwiring_b1_c1_x_0: UInt<1> | inst b1 of B - | node topwiring_b1_c1_x = UInt<1>("h0") + | wire topwiring_b1_c1_x : UInt<1> | x <= UInt(1) + | topwiring_b1_c1_x <= UInt<1>("h0") | topwiring_b1_c1_x_0 <= b1.topwiring_c1_x | module A_ : | output x: UInt<1> @@ -240,7 +242,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal x in module C" should + "The signal x in module C" should "be connected to Top port with topwiring prefix and no output function" in { val input = """circuit Top : @@ -262,8 +264,8 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output x: UInt<1> | x <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_")) val check = """circuit Top : @@ -296,7 +298,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal x in module C inst c1 and c2 and signal y in module A_" should + "The signal x in module C inst c1 and c2 and signal y in module A_" should s"be connected to Top port with topwiring prefix and outfile in $testDirName" in { val input = """circuit Top : @@ -321,11 +323,11 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output x: UInt<1> | x <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"), - TopWiringAnnotation(ComponentName(s"y", - ModuleName(s"A_", CircuitName(s"Top"))), + TopWiringAnnotation(ComponentName(s"y", + ModuleName(s"A_", CircuitName(s"Top"))), s"topwiring_"), TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)) val check = @@ -350,8 +352,9 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | module A_ : | output x: UInt<1> | output topwiring_y: UInt<1> - | node y = UInt<1>("h1") + | wire y : UInt<1> | x <= UInt(1) + | y <= UInt<1>("h1") | topwiring_y <= y | module B : | output x: UInt<1> @@ -371,7 +374,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal x in module C inst c1 and c2 and signal y in module A_" should + "The signal x in module C inst c1 and c2 and signal y in module A_" should s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in { val input = """circuit Top : @@ -396,11 +399,11 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output x: UInt<1> | x <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"), - TopWiringAnnotation(ComponentName(s"y", - ModuleName(s"A_", CircuitName(s"Top"))), + TopWiringAnnotation(ComponentName(s"y", + ModuleName(s"A_", CircuitName(s"Top"))), s"top2wiring_"), TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)) val check = @@ -425,8 +428,9 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | module A_ : | output x: UInt<1> | output top2wiring_y: UInt<1> - | node y = UInt<1>("h1") + | wire y : UInt<1> | x <= UInt(1) + | y <= UInt<1>("h1") | top2wiring_y <= y | module B : | output x: UInt<1> @@ -446,7 +450,7 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { execute(input, check, topwiringannos) } - "The signal fullword in module C inst c1 and c2 and signal y in module A_" should + "The signal fullword in module C inst c1 and c2 and signal y in module A_" should s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in { val input = """circuit Top : @@ -471,11 +475,11 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | output fullword: UInt<1> | fullword <= UInt(0) """.stripMargin - val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"fullword", - ModuleName(s"C", CircuitName(s"Top"))), + val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"fullword", + ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"), - TopWiringAnnotation(ComponentName(s"y", - ModuleName(s"A_", CircuitName(s"Top"))), + TopWiringAnnotation(ComponentName(s"y", + ModuleName(s"A_", CircuitName(s"Top"))), s"top2wiring_"), TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)) val check = @@ -500,8 +504,9 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | module A_ : | output fullword: UInt<1> | output top2wiring_y: UInt<1> - | node y = UInt<1>("h1") + | wire y : UInt<1> | fullword <= UInt(1) + | y <= UInt<1>("h1") | top2wiring_y <= y | module B : | output fullword: UInt<1> @@ -576,8 +581,9 @@ class TopWiringTests extends LowTransformSpec with TopWiringTestsCommon { | topwiring_b1_c2_fullword <= b1.topwiring_c2_fullword | module A_ : | output fullword: UInt<1> - | node y = UInt<1>("h1") + | wire y : UInt<1> | fullword <= UInt(1) + | y <= UInt<1>("h1") | module B : | output fullword: UInt<1> | output topwiring_fullword: UInt<1> |