3 files changed, 34 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index d1ff6fd1..1b0e8190 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -46,5 +46,30 @@ class CustomTransformSpec extends FirrtlFlatSpec {
 
     runFirrtlTest("CustomTransform", "/features", customTransforms = List(new ReplaceExtModuleTransform))
   }
+
+  they should "not cause \"Internal Errors\"" in {
+    val input = """
+      |circuit test :
+      |  module test :
+      |    output out : UInt
+      |    out <= UInt(123)""".stripMargin
+    val errorString = "My Custom Transform failed!"
+    class ErroringTransform extends Transform {
+      def inputForm = HighForm
+      def outputForm = HighForm
+      def execute(state: CircuitState): CircuitState = {
+        require(false, errorString)
+        state
+      }
+    }
+    val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions {
+      firrtlOptions = FirrtlExecutionOptions(
+        firrtlSource = Some(input),
+        customTransforms = List(new ErroringTransform))
+    }
+    (the [java.lang.IllegalArgumentException] thrownBy {
+      Driver.execute(optionsManager)
+    }).getMessage should include (errorString)
+  }
 }
 
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index bffb1b51..db50b491 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -135,8 +135,11 @@ circuit sram6t :
 """.stripMargin
 
     val annos = Seq(memlib.InferReadWriteAnnotation)
-    intercept[InferReadWriteCheckException] {
+    intercept[Exception] {
       compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
+    } match {
+      case CustomTransformException(_: InferReadWriteCheckException) => // success
+      case _ => fail()
     }
   }
 
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
index de84d79d..c75e0914 100644
--- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
@@ -260,16 +260,19 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
         |    m2.i <= m1.o
         |    o <= m2.o
       """.stripMargin
-    intercept[NoSuchTargetException] {
+    val e1 = the [CustomTransformException] thrownBy {
       val Top_m1 = Top.instOf("m1", "MiddleX")
       val inputState = CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Top_m1)))
       new LowFirrtlCompiler().compile(inputState, customTransforms)
     }
-    intercept[NoSuchTargetException] {
+    e1.cause shouldBe a [NoSuchTargetException]
+
+    val e2 = the [CustomTransformException] thrownBy {
       val Top_m2 = Top.instOf("x2", "Middle")
       val inputState = CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Top_m2)))
       new LowFirrtlCompiler().compile(inputState, customTransforms)
     }
+    e2.cause shouldBe a [NoSuchTargetException]
   }
 
   property("No name conflicts between two new modules") {