diff options
Diffstat (limited to 'src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala index 45be4cb3..62160e09 100644 --- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala +++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala @@ -193,4 +193,19 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec { new File(subdir, filename) should exist new File(dir, filename) shouldNot exist } + + "verilog file list" should "end with a newline" in { + val annos = Seq( + BlackBoxTargetDirAnno("test_run_dir"), + BlackBoxResourceAnno(moduleName, "/blackboxes/AdderExtModule.v") + ) + + execute(input, output, annos) + + val filename = os.pwd / "test_run_dir" / BlackBoxSourceHelper.defaultFileListName + assert(os.exists(filename), "verilog file list should exist") + val content = os.read(filename) + assert(content.contains("AdderExtModule.v")) + assert(content.last == '\n', "Some simulators like Icarus Verilog seem to expect a trailing new line character") + } } |
