diff options
Diffstat (limited to 'src/test/scala/firrtlTests/StringSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/StringSpec.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 30535466..fc2fa486 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -21,7 +21,7 @@ class PrintfSpec extends FirrtlPropSpec { copyResourceToFile(cppHarnessResourceName, harness) verilogToCpp(prefix, testDir, Seq(), harness) #&& - cppToExe(prefix, testDir) ! loggingProcessLogger + cppToExe(prefix, testDir) ! loggingProcessLogger // Check for correct Printf: // Count up from 0, match decimal, hex, and binary @@ -31,7 +31,7 @@ class PrintfSpec extends FirrtlPropSpec { var expected = 0 var error = false val ret = Process(s"./V${prefix}", testDir) ! - ProcessLogger( line => { + ProcessLogger(line => { line match { case regex(dec, hex, bin) => { if (!done) { @@ -57,7 +57,7 @@ class StringSpec extends FirrtlPropSpec { // Whitelist is [0x20 - 0x7e] val whitelist = """ !\"#$%&\''()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ""" + - """[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~""" + """[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~""" property(s"Character whitelist should be supported: [$whitelist] ") { val lit = StringLit.unescape(whitelist) @@ -102,7 +102,7 @@ class StringSpec extends FirrtlPropSpec { val legalFormats = "HhDdOoBbCcLlVvMmSsTtUuZz%".toSet def isValidVerilogFormat(str: String): Boolean = str.toSeq.sliding(2).forall { case Seq('%', char) if legalFormats contains char => true - case _ => true + case _ => true } // Generators for legal Firrtl format strings @@ -112,8 +112,8 @@ class StringSpec extends FirrtlPropSpec { val genFragment = Gen.frequency((10, genChar), (1, genFormat), (1, genEsc)).map(_.mkString) val genString = Gen.listOf[String](genFragment).map(_.mkString) - property ("Firrtl Format Strings with Unicode chars should emit as legal Verilog Strings") { - forAll (genString) { str => + property("Firrtl Format Strings with Unicode chars should emit as legal Verilog Strings") { + forAll(genString) { str => val verilogStr = StringLit(str).verilogFormat.verilogEscape assert(isValidVerilogString(verilogStr)) assert(isValidVerilogFormat(verilogStr)) |