diff options
Diffstat (limited to 'src/test/scala/firrtlTests/MemSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/MemSpec.scala | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/MemSpec.scala b/src/test/scala/firrtlTests/MemSpec.scala index c7ab8db7..e05aca86 100644 --- a/src/test/scala/firrtlTests/MemSpec.scala +++ b/src/test/scala/firrtlTests/MemSpec.scala @@ -50,7 +50,7 @@ class MemSpec extends FirrtlPropSpec with FirrtlMatchers { """.stripMargin val result = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm, List.empty)) // TODO Not great that it includes the sparse comment for VCS - result should containLine (s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize-1}];") + result should containLine(s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize - 1}];") } property("Very large CHIRRTL memories should be supported") { @@ -76,7 +76,6 @@ class MemSpec extends FirrtlPropSpec with FirrtlMatchers { """.stripMargin val result = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm, List.empty)) // TODO Not great that it includes the sparse comment for VCS - result should containLine (s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize-1}];") + result should containLine(s"reg /* sparse */ [7:0] m [0:$addrWidth'd${memSize - 1}];") } } - |