diff options
Diffstat (limited to 'src/test/resources/features')
| -rw-r--r-- | src/test/resources/features/ChirrtlMems.fir | 16 | ||||
| -rw-r--r-- | src/test/resources/features/CustomTransform.fir | 16 | ||||
| -rw-r--r-- | src/test/resources/features/NestedSubAccessTester.fir | 8 | ||||
| -rw-r--r-- | src/test/resources/features/Printf.fir | 10 | ||||
| -rw-r--r-- | src/test/resources/features/ZeroPortMem.fir | 8 |
5 files changed, 29 insertions, 29 deletions
diff --git a/src/test/resources/features/ChirrtlMems.fir b/src/test/resources/features/ChirrtlMems.fir index 6cc9f122..c51e3b78 100644 --- a/src/test/resources/features/ChirrtlMems.fir +++ b/src/test/resources/features/ChirrtlMems.fir @@ -1,22 +1,22 @@ ; See LICENSE for license details. circuit ChirrtlMems : module ChirrtlMems : - input clk : Clock + input clock : Clock input reset : UInt<1> cmem ram : UInt<32>[16] - node newClock = clk + node newClock = clock wire wen : UInt<1> wen <= not(reset) ; Don't const prop me! - reg raddr : UInt<4>, clk with : (reset => (reset, UInt(0))) + reg raddr : UInt<4>, clock with : (reset => (reset, UInt(0))) raddr <= add(raddr, UInt(1)) infer mport r = ram[raddr], newClock when wen : - node newerClock = clk - reg waddr : UInt<4>, clk with : (reset => (reset, UInt(0))) + node newerClock = clock + reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0))) waddr <= add(waddr, UInt(1)) infer mport w = ram[waddr], newerClock w <= waddr @@ -27,8 +27,8 @@ circuit ChirrtlMems : when not(reset) : when gt(waddr, UInt(1)) : when neq(r, raddr) : - printf(clk, UInt(1), "Assertion failed! r =/= raddr\n") - stop(clk, UInt(1), 1) ; Failure! + printf(clock, UInt(1), "Assertion failed! r =/= raddr\n") + stop(clock, UInt(1), 1) ; Failure! when eq(raddr, UInt(15)) : - stop(clk, UInt(1), 0) ; Success! + stop(clock, UInt(1), 0) ; Success! diff --git a/src/test/resources/features/CustomTransform.fir b/src/test/resources/features/CustomTransform.fir index 61bd6ad2..de00f261 100644 --- a/src/test/resources/features/CustomTransform.fir +++ b/src/test/resources/features/CustomTransform.fir @@ -2,21 +2,21 @@ circuit CustomTransform : ; Replaced in custom transform by an implementation extmodule Delay : - input clk : Clock + input clock : Clock input reset : UInt<1> input a : UInt<32> input en : UInt<1> output b : UInt<32> module CustomTransform : - input clk : Clock + input clock : Clock input reset : UInt<1> - reg cycle : UInt<32>, clk with : (reset => (reset, UInt<32>(0))) + reg cycle : UInt<32>, clock with : (reset => (reset, UInt<32>(0))) cycle <= tail(add(cycle, UInt<32>(1)), 1) inst delay of Delay - delay.clk <= clk + delay.clock <= clock delay.reset <= reset delay.a <= UInt(0) delay.en <= UInt(0) @@ -26,9 +26,9 @@ circuit CustomTransform : delay.a <= UInt("hdeadbeef") when eq(cycle, UInt(1)) : when neq(delay.b, UInt("hdeadbeef")) : - printf(clk, UInt(1), "Assertion failed!\n") - stop(clk, UInt(1), 1) + printf(clock, UInt(1), "Assertion failed!\n") + stop(clock, UInt(1), 1) when eq(cycle, UInt(2)) : - printf(clk, UInt(1), "Success!\n") - stop(clk, UInt(1), 0) + printf(clock, UInt(1), "Success!\n") + stop(clock, UInt(1), 0) diff --git a/src/test/resources/features/NestedSubAccessTester.fir b/src/test/resources/features/NestedSubAccessTester.fir index c40da6a0..84b4cfbe 100644 --- a/src/test/resources/features/NestedSubAccessTester.fir +++ b/src/test/resources/features/NestedSubAccessTester.fir @@ -12,7 +12,7 @@ circuit NestedSubAccessTester : out <= vec[foo[index]] module NestedSubAccessTester : - input clk : Clock + input clock : Clock input reset : UInt<1> inst dut of NestedSubAccess @@ -22,9 +22,9 @@ circuit NestedSubAccessTester : dut.foo[2] <= UInt(1) when neq(dut.out, UInt(4)) : - printf(clk, not(reset), "Assertion failed\nTest Failed!\n") - stop(clk, not(reset), 1) + printf(clock, not(reset), "Assertion failed\nTest Failed!\n") + stop(clock, not(reset), 1) else : - stop(clk, not(reset), 0) + stop(clock, not(reset), 0) diff --git a/src/test/resources/features/Printf.fir b/src/test/resources/features/Printf.fir index a19e2493..5e065b9c 100644 --- a/src/test/resources/features/Printf.fir +++ b/src/test/resources/features/Printf.fir @@ -1,17 +1,17 @@ ; See LICENSE for license details. circuit Printf : module Printf : - input clk : Clock + input clock : Clock input reset : UInt<1> - reg count : UInt<10>, clk with : + reg count : UInt<10>, clock with : reset => (reset, UInt<6>(0)) - reg const : UInt<32> clk with : + reg const : UInt<32> clock with : reset => (reset, UInt(123456)) node notReset = not(reset) count <= add(count, UInt(1)) - printf(clk, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const) + printf(clock, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const) when eq(count, UInt(255)) : - stop(clk, UInt(1), 0) + stop(clock, UInt(1), 0) diff --git a/src/test/resources/features/ZeroPortMem.fir b/src/test/resources/features/ZeroPortMem.fir index 7e509ecf..96327f5c 100644 --- a/src/test/resources/features/ZeroPortMem.fir +++ b/src/test/resources/features/ZeroPortMem.fir @@ -1,7 +1,7 @@ ; See LICENSE for license details. circuit ZeroPortMem : module ZeroPortMem : - input clk : Clock + input clock : Clock input reset : UInt<1> mem mymem : @@ -16,8 +16,8 @@ circuit ZeroPortMem : when not(reset) : when eq(foo, UInt<32>("hdeadbeef")) : - stop(clk, UInt(1), 0) ; Success ! + stop(clock, UInt(1), 0) ; Success ! else : - printf(clk, UInt(1), "Assertion failed!\n") - stop(clk, UInt(1), 1) ; Failure! + printf(clock, UInt(1), "Assertion failed!\n") + stop(clock, UInt(1), 1) ; Failure! |