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-rw-r--r--src/main/scala/firrtl/passes/ExpandWhens.scala20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 560a1c1c..956d54bc 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -73,7 +73,13 @@ object ExpandWhens extends Pass {
def expandWhens(m: Module): (Netlist, Simlist, Seq[Attach], Statement, InfoMap) = {
val namespace = Namespace(m)
val simlist = new Simlist
+
+ // Memoizes if an expression contains any WVoids inserted in this pass
+ val memoizedVoid = new mutable.HashSet[MemoizedHash[Expression]] += WVoid
+
+ // Memoizes the node that holds a particular expression, if any
val nodes = new NodeMap
+
// Seq of attaches in order
lazy val attaches = mutable.ArrayBuffer.empty[Attach]
@@ -171,7 +177,21 @@ object ExpandWhens extends Pass {
conseqNetlist getOrElse (lvalue, altNetlist(lvalue))
}
+ // Does an expression contain WVoid inserted in this pass?
+ def containsVoid(e: Expression): Boolean = e match {
+ case WVoid => true
+ case ValidIf(_, value, _) => memoizedVoid(value)
+ case Mux(_, tv, fv, _) => memoizedVoid(tv) || memoizedVoid(fv)
+ case _ => false
+ }
+
res match {
+ // Don't create a node to hold mux trees with void values
+ // "Idiomatic" emission of these muxes isn't a concern because they represent bad code (latches)
+ case e if containsVoid(e) =>
+ netlist(lvalue) = e
+ memoizedVoid += e // remember that this was void
+ EmptyStmt
case _: ValidIf | _: Mux | _: DoPrim => nodes get res match {
case Some(name) =>
netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE)