diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 10d3ae85..b1c318fa 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -148,7 +148,11 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em emitAllModules(state.circuit) map (EmittedFirrtlModuleAnnotation(_)) case _ => Seq() } - state.copy(annotations = Some(AnnotationMap(newAnnos))) + val annos = newAnnos ++ (state.annotations match { + case None => Seq.empty + case Some(a) => a.annotations + }) + state.copy(annotations = Some(AnnotationMap(annos))) } // Old style, deprecated @@ -775,6 +779,10 @@ class VerilogEmitter extends Transform with PassBased with Emitter { } case _ => Seq() } - state.copy(annotations = Some(AnnotationMap(newAnnos))) + val annos = newAnnos ++ (state.annotations match { + case None => Seq.empty + case Some(a) => a.annotations + }) + state.copy(annotations = Some(AnnotationMap(annos))) } } |
