diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/ExecutionOptionsManager.scala | 10 | ||||
| -rw-r--r-- | src/main/scala/firrtl/transforms/Dedup.scala | 12 |
2 files changed, 19 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala index 47083cb4..189701dc 100644 --- a/src/main/scala/firrtl/ExecutionOptionsManager.scala +++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala @@ -7,6 +7,7 @@ import firrtl.Parser._ import firrtl.ir.Circuit import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation} import firrtl.passes.clocklist.ClockListAnnotation +import firrtl.transforms.NoCircuitDedupAnnotation import logger.LogLevel import scopt.OptionParser @@ -476,6 +477,15 @@ trait HasFirrtlOptions { "Do NOT run dead code elimination" } + parser.opt[Unit]("no-dedup") + .foreach { _ => + firrtlOptions = firrtlOptions.copy( + annotations = firrtlOptions.annotations :+ NoCircuitDedupAnnotation + ) + }.text { + "Do NOT dedup modules" + } + parser.note("") } diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 83daad7f..609b5935 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -20,6 +20,8 @@ case class NoDedupAnnotation(target: ModuleName) extends SingleTargetAnnotation[ def duplicate(n: ModuleName): NoDedupAnnotation = NoDedupAnnotation(n) } +case object NoCircuitDedupAnnotation extends NoTargetAnnotation + /** Only use on legal Firrtl. * * Specifically, the restriction of instance loops must have been checked, or else this pass can @@ -34,9 +36,13 @@ class DedupModules extends Transform { * @return A transformed Firrtl AST */ def execute(state: CircuitState): CircuitState = { - val noDedups = state.annotations.collect { case NoDedupAnnotation(ModuleName(m, c)) => m } - val (newC, renameMap) = run(state.circuit, noDedups, state.annotations) - state.copy(circuit = newC, renames = Some(renameMap)) + if (state.annotations.contains(NoCircuitDedupAnnotation)) { + state + } else { + val noDedups = state.annotations.collect { case NoDedupAnnotation(ModuleName(m, c)) => m } + val (newC, renameMap) = run(state.circuit, noDedups, state.annotations) + state.copy(circuit = newC, renames = Some(renameMap)) + } } /** Deduplicates a circuit, and records renaming |
