diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index ce222b6e..000419cc 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2608,7 +2608,7 @@ defn emit-verilog (m:InModule) -> Module : emit(["module " name(m) "("]) if !empty?(portdefs) : for (x in portdefs, i in 0 to false) do : - if i != length(portdefs) : emit([tab x ","]) + if i != length(portdefs) - 1 : emit([tab x ","]) else : emit([tab x]) emit([");"]) |