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-rw-r--r--src/main/scala/firrtl/passes/ZeroWidth.scala27
1 files changed, 9 insertions, 18 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index e918ff63..003ab3c9 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -25,19 +25,12 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
case _ => false
}
- private def makeEmptyMemBundle(name: String): Field =
- Field(
- name,
- Flip,
- BundleType(
- Seq(
- Field("addr", Default, UIntType(IntWidth(0))),
- Field("en", Default, UIntType(IntWidth(0))),
- Field("clk", Default, UIntType(IntWidth(0))),
- Field("data", Flip, UIntType(IntWidth(0)))
- )
- )
- )
+ private def makeZero(tpe: ir.Type): ir.Type = tpe match {
+ case ClockType => UIntType(IntWidth(0))
+ case a: UIntType => a.copy(IntWidth(0))
+ case a: SIntType => a.copy(IntWidth(0))
+ case a: AggregateType => a.map(makeZero)
+ }
private def onEmptyMemStmt(s: Statement): Statement = s match {
case d @ DefMemory(info, name, tpe, _, _, _, rs, ws, rws, _) =>
@@ -46,11 +39,9 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
DefWire(
info,
name,
- BundleType(
- rs.map(r => makeEmptyMemBundle(r)) ++
- ws.map(w => makeEmptyMemBundle(w)) ++
- rws.map(rw => makeEmptyMemBundle(rw))
- )
+ MemPortUtils
+ .memType(d)
+ .map(makeZero)
)
case Some(_) => d
}