3 files changed, 19 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 7fdf0bfc..7b77e324 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -30,6 +30,11 @@ object EmitCircuitAnnotation extends HasShellOptions {
         a match {
           case "chirrtl" =>
             Seq(RunFirrtlTransformAnnotation(new ChirrtlEmitter), EmitCircuitAnnotation(classOf[ChirrtlEmitter]))
+          case "mhigh" =>
+            Seq(
+              RunFirrtlTransformAnnotation(new MinimumHighFirrtlEmitter),
+              EmitCircuitAnnotation(classOf[MinimumHighFirrtlEmitter])
+            )
           case "high" =>
             Seq(RunFirrtlTransformAnnotation(new HighFirrtlEmitter), EmitCircuitAnnotation(classOf[HighFirrtlEmitter]))
           case "middle" =>
@@ -69,6 +74,11 @@ object EmitAllModulesAnnotation extends HasShellOptions {
         a match {
           case "chirrtl" =>
             Seq(RunFirrtlTransformAnnotation(new ChirrtlEmitter), EmitAllModulesAnnotation(classOf[ChirrtlEmitter]))
+          case "mhigh" =>
+            Seq(
+              RunFirrtlTransformAnnotation(new MinimumHighFirrtlEmitter),
+              EmitAllModulesAnnotation(classOf[MinimumHighFirrtlEmitter])
+            )
           case "high" =>
             Seq(
               RunFirrtlTransformAnnotation(new HighFirrtlEmitter),
diff --git a/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala b/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
index 80aea996..bb385ffd 100644
--- a/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
+++ b/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
@@ -61,6 +61,13 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
 }
 
 class ChirrtlEmitter extends FirrtlEmitter(CircuitForm.ChirrtlForm)
+class MinimumHighFirrtlEmitter extends FirrtlEmitter(CircuitForm.HighForm) {
+  override def prerequisites = stage.Forms.MinimalHighForm
+  override def optionalPrerequisites = Seq.empty
+  override def optionalPrerequisiteOf = Seq.empty
+  override def invalidates(a: Transform) = false
+  override val outputSuffix = ".mhi.fir"
+}
 class HighFirrtlEmitter extends FirrtlEmitter(CircuitForm.HighForm)
 class MiddleFirrtlEmitter extends FirrtlEmitter(CircuitForm.MidForm)
 class LowFirrtlEmitter extends FirrtlEmitter(CircuitForm.LowForm)
diff --git a/src/main/scala/firrtl/stage/FirrtlAnnotations.scala b/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
index 44c88418..8f5ee3e1 100644
--- a/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
+++ b/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
@@ -164,7 +164,7 @@ object CompilerAnnotation extends HasShellOptions {
       toAnnotationSeq = a => Seq(RunFirrtlTransformAnnotation.stringToEmitter(a)),
       helpText = "The FIRRTL compiler to use (default: verilog)",
       shortOption = Some("X"),
-      helpValueName = Some("<none|high|middle|low|verilog|mverilog|sverilog>")
+      helpValueName = Some("<none|mhigh|high|middle|low|verilog|mverilog|sverilog>")
     )
   )
 
@@ -185,6 +185,7 @@ object RunFirrtlTransformAnnotation extends HasShellOptions {
   private[firrtl] def stringToEmitter(a: String): RunFirrtlTransformAnnotation = {
     val emitter = a match {
       case "none"     => new ChirrtlEmitter
+      case "mhigh"    => new MinimumHighFirrtlEmitter
       case "high"     => new HighFirrtlEmitter
       case "low"      => new LowFirrtlEmitter
       case "middle"   => new MiddleFirrtlEmitter