diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 3bbba289..27348c6a 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -204,7 +204,15 @@ class VerilogEmitter extends SeqTransform with Emitter { } /** Turn Params into Verilog Strings */ def stringify(param: Param): String = param match { - case IntParam(name, value) => s".$name($value)" + case IntParam(name, value) => + val lit = + if (value.isValidInt) { + s"$value" + } else { + val blen = value.bitLength + if (value > 0) s"$blen'd$value" else s"-${blen+1}'sd${value.abs}" + } + s".$name($lit)" case DoubleParam(name, value) => s".$name($value)" case StringParam(name, value) => s".${name}(${value.verilogEscape})" case RawStringParam(name, value) => s".$name($value)" |