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Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/GroupComponents.scala | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 439a1642..55828e0a 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -181,7 +181,11 @@ class GroupComponents extends firrtl.Transform { def punchSignalOut(group: String, exp: Expression): String = { val portName = addPort(group, exp, Output) - groupStatements(group) += Connect(NoInfo, WRef(portName), exp) + val connectStatement = exp.tpe match { + case AnalogType(_) => Attach(NoInfo, Seq(WRef(portName), exp)) + case _ => Connect(NoInfo, WRef(portName), exp) + } + groupStatements(group) += connectStatement portName } |