diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/firrtl/proto/FromProto.scala | 8 |
2 files changed, 6 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index cd801570..61fd6258 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -10,8 +10,6 @@ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.options.Dependency -import scala.collection.mutable - case class MPort(name: String, clk: Expression) case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean) @@ -82,14 +80,14 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration { types(sx.name) = sx.tpe val taddr = UIntType(IntWidth(1 max getUIntWidth(sx.size - 1))) val tdata = sx.tpe - def set_poison(vec: mutable.Seq[MPort]) = vec.toSeq.flatMap (r => Seq( + def set_poison(vec: scala.collection.Seq[MPort]) = vec.toSeq.flatMap (r => Seq( IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "addr", taddr)), IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "clk", ClockType)) )) - def set_enable(vec: mutable.Seq[MPort], en: String) = vec.toSeq.map (r => + def set_enable(vec: scala.collection.Seq[MPort], en: String) = vec.toSeq.map (r => Connect(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), en, BoolType), zero) ) - def set_write(vec: mutable.Seq[MPort], data: String, mask: String) = vec.toSeq.flatMap { r => + def set_write(vec: scala.collection.Seq[MPort], data: String, mask: String) = vec.toSeq.flatMap { r => val tmask = createMask(sx.tpe) val portRef = SubField(Reference(sx.name, ut), r.name, ut) Seq(IsInvalid(sx.info, SubField(portRef, data, tdata)), IsInvalid(sx.info, SubField(portRef, mask, tmask))) diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala index dced9c2d..41a7e1de 100644 --- a/src/main/scala/firrtl/proto/FromProto.scala +++ b/src/main/scala/firrtl/proto/FromProto.scala @@ -10,8 +10,6 @@ import FirrtlProtos._ import com.google.protobuf.CodedInputStream import Firrtl.Statement.{Formal, ReadUnderWrite} -import scala.collection.mutable - object FromProto { /** Deserialize ProtoBuf representation of [[ir.Circuit]] @@ -36,9 +34,9 @@ object FromProto { } // Convert from ProtoBuf message repeated Statements to FIRRRTL Block - private def compressStmts(stmts: mutable.Seq[ir.Statement]): ir.Statement = stmts match { - case mutable.Seq() => ir.EmptyStmt - case mutable.Seq(stmt) => stmt + private def compressStmts(stmts: scala.collection.Seq[ir.Statement]): ir.Statement = stmts match { + case scala.collection.Seq() => ir.EmptyStmt + case scala.collection.Seq(stmt) => stmt case multiple => ir.Block(multiple.toSeq) } |