diff options
Diffstat (limited to 'src/main/stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 3 | ||||
| -rw-r--r-- | src/main/stanza/errors.stanza | 6 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 4 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 21 | ||||
| -rw-r--r-- | src/main/stanza/verilog.stanza | 84 |
5 files changed, 64 insertions, 54 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index b87c654e..d65e7718 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -78,12 +78,13 @@ public defn run-passes (c:Circuit,ls:List<Pass>) : if PRINT-CIRCUITS : print(c) val start-time = current-time-us() var t = start-time + val tables = Vector<HashTable<Symbol,HashTable<Symbol,Symbol>>>() for p in ls do : if PRINT-CIRCUITS : println(name(p)) c* = pass(p)(c*) if PRINT-CIRCUITS : print(c*) - if PRINT-CIRCUITS : println-all(["Finished " name(p) "\n"]) val current-time = current-time-us() + println-all(["Finished " name(p) "\n"]) println-all(["Time since start: " current-time - start-time]) println-all(["Time for this pass: " current-time - t]) t = current-time diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 608b47d2..e36ec06d 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -774,7 +774,7 @@ public defn check-low-form (c:Circuit) -> Circuit : for p in ports(m) do : check-low-form-t(info(p),type(p),name(p)) - val assigned? = Vector<Symbol>() + val assigned? = HashTable<Symbol,True>(symbol-hash) val insts = Vector<Symbol>() val mems = Vector<Symbol>() defn check-correct-exp (info:FileInfo,e:Expression) -> False : @@ -811,8 +811,8 @@ public defn check-low-form (c:Circuit) -> Circuit : match(loc(s)) : (e:Ref|Subfield) : val n* = to-symbol $ to-string $ e - if contains?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*)) - else : add(assigned?,to-symbol $ to-string $ e) + if key?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*)) + else : assigned?[to-symbol $ to-string $ e] = true (e) : check-correct-exp(info(s),e) (s:EmptyStmt) : false (s:Begin) : do(check-low-form-s,s) diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index b37e974f..e57c5f74 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -5,8 +5,8 @@ defpackage firrtl/ir2 : public defmulti info! (x:?) -> FileInfo public defmethod info! (x:?) : FileInfo() -public val vector-expand-delin = `_ -public val bundle-expand-delin = `_ +public val vector-expand-delin = `$ +public val bundle-expand-delin = `$ public val scope-delin = `% public val temp-delin = `! public val inline-delin = `^ diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 99679cf6..c03e2194 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -285,7 +285,7 @@ defmethod map (f: Type -> Type, e: WIndex) : ; Returns a new Circuit where all names have all special characters ; removed, except _. -public defstruct RemoveSpecialChars <: Pass +public defstruct RemoveSpecialChars <: Pass public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters" public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" @@ -294,12 +294,12 @@ public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" defn get-new-string (n:Char) -> String : switch {n == _} : - '_' : "__" + ;'_' : "__" '~' : "_A" '!' : "_B" '@' : "_C" '#' : "_D" - '$' : "_E" + ;'$' : "_E" '%' : "_F" '^' : "_G" '*' : "_H" @@ -1020,10 +1020,11 @@ defn lower (body:Stmt) -> Stmt : (s:DefAccessor) : val ls = generate-entry(name(s),type(s)) val rs = generate-entry(name(source(s) as WRef),type(s)) + val index* = exp(head $ expand-expr(index(s))) Begin $ for (l in ls, r in rs) map: if flip(r) == REVERSE : error("Shouldn't be here") val memref = WRef(name(r),VectorType(type(r),size(s)),MemKind(),gender(s)) - DefAccessor(info(s),name(l),memref,index(s),to-acc-dir(gender(s))) + DefAccessor(info(s),name(l),memref,index*,to-acc-dir(gender(s))) (s:OnReset|Connect) : Begin $ for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map : val lgender = FEMALE * flip(l) @@ -1063,6 +1064,7 @@ defn lower (body:Stmt) -> Stmt : [MALE,FEMALE] : Connect(info(s),r*,l*) (s:ConnectFromIndexed) : Begin(ls) where : val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash) + val index* = exp(head $ expand-expr(index(s))) for e in exps(s) do : for (r in expand-expr(e),l in expand-expr(loc(s))) do : val n = name(exp(l) as WRef) @@ -1078,10 +1080,11 @@ defn lower (body:Stmt) -> Stmt : val l* = set-gender(exp(l),lgender,flip(l)) val exps = to-list $ for e in ctable[n] map : set-gender(exp(e),rgender,flip(e)) switch fn ([x,y]) : lgender == x and rgender == y : - [FEMALE,MALE] : ConnectFromIndexed(info(s),index(s),l*,exps) - [MALE,FEMALE] : ConnectToIndexed(info(s),index(s),exps,l*) + [FEMALE,MALE] : ConnectFromIndexed(info(s),index*,l*,exps) + [MALE,FEMALE] : ConnectToIndexed(info(s),index*,exps,l*) (s:ConnectToIndexed) : Begin(ls) where : val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash) + val index* = exp(head $ expand-expr(index(s))) for e in locs(s) do : for (l in expand-expr(e),r in expand-expr(exp(s))) do : val n = name(exp(r) as WRef) @@ -1097,8 +1100,8 @@ defn lower (body:Stmt) -> Stmt : val r* = set-gender(exp(r),rgender,flip(r)) val locs = to-list $ for e in ctable[n] map : set-gender(exp(e),lgender,flip(e)) switch fn ([x,y]) : lgender == x and rgender == y : - [FEMALE,MALE] : ConnectToIndexed(info(s),index(s),locs,r*) - [MALE,FEMALE] : ConnectFromIndexed(info(s),index(s),r*,locs) + [FEMALE,MALE] : ConnectToIndexed(info(s),index*,locs,r*) + [MALE,FEMALE] : ConnectFromIndexed(info(s),index*,r*,locs) (s:Conditionally) : Conditionally(info(s),exp(head $ expand-expr(pred(s))),lower-stmt(conseq(s)),lower-stmt(alt(s))) (s:Begin|EmptyStmt) : map(lower-stmt,s) @@ -2074,7 +2077,7 @@ defn split-exp (c:Circuit) : do(f,s) (s:Connect) : val exp* = map(split-exp-e{_,full-name(loc(s)),info(s)},exp(s)) - add(v,Connect(info(s),loc(s),exp(s))) + add(v,Connect(info(s),loc(s),exp*)) (s:DefNode) : val exp* = map(split-exp-e{_,name(s),info(s)},value(s)) add(v,DefNode(info(s),name(s),exp*)) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 29112271..8d6bfecf 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -66,25 +66,27 @@ defn emit (e:Expression) -> String : (e:Subfield) : error("Non-supported expression") (e:Index) : error("Non-supported expression") (e:DoPrim) : - val sargs = map(emit-as-type{_,type(e)},args(e)) - val xargs = map(emit-signed-if-any{_,args(e)},args(e)) + ;val sargs = map(emit-as-type{_,type(e)},args(e)) + ;val xargs = map(emit-signed-if-any{_,args(e)},args(e)) string-join $ switch {_ == op(e)} : - ADD-OP : [sargs[0] " + " sargs[1]] - SUB-OP : [sargs[0] " - " sargs[1]] - MUL-OP : [sargs[0] " * " sargs[1] ] - DIV-OP : [sargs[0] " / " sargs[1] ] - MOD-OP : [sargs[0] " % " sargs[1] ] - QUO-OP : [sargs[0] " / " sargs[1] ] - REM-OP : [sargs[0] " % " sargs[1] ] - ADD-WRAP-OP : [sargs[0], " + " sargs[1]] - SUB-WRAP-OP : [sargs[0], " - " sargs[1]] - LESS-OP : [xargs[0] " < " xargs[1]] - LESS-EQ-OP : [xargs[0] " <= " xargs[1]] - GREATER-OP : [xargs[0] " > " xargs[1]] - GREATER-EQ-OP : [xargs[0] " >= " xargs[1]] - NEQUAL-OP : [xargs[0] " != " xargs[1]] - EQUAL-OP : [xargs[0] " == " xargs[1]] - MUX-OP : [emit(args(e)[0]) " ? " sargs[1] " : " sargs[2]] + ADD-OP : [emit-as-type(args(e)[0],type(e)) " + " emit-as-type(args(e)[1],type(e))] + SUB-OP : [emit-as-type(args(e)[0],type(e)) " - " emit-as-type(args(e)[1],type(e))] + MUL-OP : [emit-as-type(args(e)[0],type(e)) " * " emit-as-type(args(e)[1],type(e)) ] + DIV-OP : [emit-as-type(args(e)[0],type(e)) " / " emit-as-type(args(e)[1],type(e)) ] + MOD-OP : [emit-as-type(args(e)[0],type(e)) " % " emit-as-type(args(e)[1],type(e)) ] + QUO-OP : [emit-as-type(args(e)[0],type(e)) " / " emit-as-type(args(e)[1],type(e)) ] + REM-OP : [emit-as-type(args(e)[0],type(e)) " % " emit-as-type(args(e)[1],type(e)) ] + ADD-WRAP-OP : [emit-as-type(args(e)[0],type(e)), " + " emit-as-type(args(e)[1],type(e))] + SUB-WRAP-OP : [emit-as-type(args(e)[0],type(e)), " - " emit-as-type(args(e)[1],type(e))] + LESS-OP : [emit-signed-if-any(args(e)[0],args(e)) " < " emit-signed-if-any(args(e)[1],args(e))] + LESS-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " <= " emit-signed-if-any(args(e)[1],args(e))] + GREATER-OP : [emit-signed-if-any(args(e)[0],args(e)) " > " emit-signed-if-any(args(e)[1],args(e))] + GREATER-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " >= " emit-signed-if-any(args(e)[1],args(e))] + NEQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))] + EQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))] + MUX-OP : + val en = emit(args(e)[0]) + [en " ? " emit-as-type(args(e)[1],type(e)) " : " emit-as-type(args(e)[2],type(e))] PAD-OP : val x = args(e)[0] val w = width!(type(x)) @@ -97,43 +99,42 @@ defn emit (e:Expression) -> String : ["$unsigned(" emit(args(e)[0]) ")"] AS-SINT-OP : ["$signed(" emit(args(e)[0]) ")"] - DYN-SHIFT-LEFT-OP : [sargs[0] " << " emit(args(e)[1])] + DYN-SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " emit(args(e)[1])] DYN-SHIFT-RIGHT-OP : - if type(e) typeof SIntType : [sargs[0] " >>> " emit(args(e)[1])] - else : [sargs[0] " >> " emit(args(e)[1])] - SHIFT-LEFT-OP : [sargs[0] " << " consts(e)[0]] + if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " emit(args(e)[1])] + else : [emit-as-type(args(e)[0],type(e)) " >> " emit(args(e)[1])] + SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " consts(e)[0]] SHIFT-RIGHT-OP : - if type(e) typeof SIntType : [sargs[0] " >>> " consts(e)[0]] - else : [sargs[0] " >> " consts(e)[0]] - NEG-OP : ["-{" sargs[0] "}"] + if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " consts(e)[0]] + else : [emit-as-type(args(e)[0],type(e)) " >> " consts(e)[0]] + NEG-OP : ["-{" emit-as-type(args(e)[0],type(e)) "}"] CONVERT-OP : match(type(args(e)[0])) : - (t:UIntType) : ["{1'b0," sargs[0] "}"] - (t:SIntType) : [sargs[0]] - BIT-NOT-OP : ["!" sargs[0]] - BIT-AND-OP : [sargs[0] " & " sargs[1]] - BIT-OR-OP : [sargs[0] " | " sargs[1]] - BIT-XOR-OP : [sargs[0] " ^ " sargs[1]] - CONCAT-OP : ["{" sargs[0] "," sargs[1] "}"] - BIT-SELECT-OP : [sargs[0] "[" consts(e)[0] "]"] - BITS-SELECT-OP : [sargs[0] "[" consts(e)[0] ":" consts(e)[1] "]"] + (t:UIntType) : ["{1'b0," emit-as-type(args(e)[0],type(e)) "}"] + (t:SIntType) : [emit-as-type(args(e)[0],type(e))] + BIT-NOT-OP : ["!" emit-as-type(args(e)[0],type(e))] + BIT-AND-OP : [emit-as-type(args(e)[0],type(e)) " & " emit-as-type(args(e)[1],type(e))] + BIT-OR-OP : [emit-as-type(args(e)[0],type(e)) " | " emit-as-type(args(e)[1],type(e))] + BIT-XOR-OP : [emit-as-type(args(e)[0],type(e)) " ^ " emit-as-type(args(e)[1],type(e))] + CONCAT-OP : ["{" emit-as-type(args(e)[0],type(e)) "," emit-as-type(args(e)[1],type(e)) "}"] + BIT-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] "]"] + BITS-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] ":" consts(e)[1] "]"] BIT-AND-REDUCE-OP : - var v = sargs[0] + var v = emit-as-type(args(e)[0],type(e)) for x in tail(args(e)) do : v = concat(v, [" & " emit(x)]) v BIT-OR-REDUCE-OP : - var v = sargs[0] + var v = emit-as-type(args(e)[0],type(e)) for x in tail(args(e)) do : v = concat(v, [" | " emit(x)]) v BIT-XOR-REDUCE-OP : - var v = sargs[0] + var v = emit-as-type(args(e)[0],type(e)) for x in tail(args(e)) do : v = concat(v, [" ^ " emit(x)]) v - defn get-name (e:Expression) -> Symbol : match(e) : (e:Ref) : name(e) @@ -184,20 +185,25 @@ defn emit-module (m:InModule) : val my-clk-update = get?(updates,get-name(clock(s)),Vector<Streamable>()) if key?(ens,sym) : add(my-clk-update,["if(" emit(ens[sym]) ") begin"]) - add(my-clk-update,[" " sym " <= " emit(cons[sym]) ";"]) + val x = cons[sym] + val y = emit(x) + add(my-clk-update,[" " sym " <= " y ";"]) add(my-clk-update,["end"]) else : add(my-clk-update,[sym " <= " emit(cons[sym]) ";"]) updates[get-name(clock(s))] = my-clk-update (s:DefMemory) : + println(STANDARD-ERROR, s) val vtype = type(s) as VectorType add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) add(inits,[" " sym "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : + println(STANDARD-ERROR, s) add(wires,["wire " get-width(type(value(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(value(s)) ";"]) (s:DefInstance) : + println(STANDARD-ERROR, s) inst-ports[sym] = Vector<Streamable>() insts[sym] = name(module(s) as Ref) for f in fields(type(module(s)) as BundleType) do : |