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-rw-r--r--src/main/stanza/compilers.stanza8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 3ca4f8da..0d0191bf 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -78,8 +78,6 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
;===============
ConstProp()
;===============
- SplitExp()
- ;===============
ResolveKinds()
InferTypes()
CheckTypes()
@@ -98,6 +96,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
InferWidths()
CheckWidths()
;===============
+ VerilogWrap()
+ SplitExp()
VerilogRename()
Verilog(with-output(c))
;===============
@@ -152,8 +152,6 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
;===============
ConstProp()
;===============
- SplitExp()
- ;===============
ResolveKinds()
InferTypes()
CheckTypes()
@@ -172,6 +170,8 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
InferWidths()
CheckWidths()
;===============
+ SplitExp()
+ ;===============
FIRRTL(with-output(c))
]