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-rw-r--r--src/main/scala/firrtl/passes/wiring/Wiring.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 1ee509e2..c62a565e 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -196,7 +196,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
case Block(sx) => sx
case s => Seq(s)
}
- Module(i, n, ps ++ ports, Block(defines ++ stmts ++ connects))
+ Module(i, n, ps ++ ports, Block(List() ++ defines ++ stmts ++ connects))
case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p)
}
}