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-rw-r--r--src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index 3139ef21..5fc99b9c 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -109,7 +109,8 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
def defaultConnects(wrapperPort: WRef, bbPort: WSubField): Seq[Connect] =
Seq("clk", "en", "addr") map (f => connectFields(bbPort, f, wrapperPort, f))
- // Connects the clk, en, and addr fields from the wrapperPort to the bbPort
+ // Generates mask bits (concatenates an aggregate to ground type)
+ // depending on mask granularity (# bits = data width / mask granularity)
def maskBits(mask: WSubField, dataType: Type, fillMask: Boolean): Expression =
if (fillMask) toBitMask(mask, dataType) else toBits(mask)