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-rw-r--r--src/main/scala/firrtl/passes/VerilogRename.scala11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogRename.scala b/src/main/scala/firrtl/passes/VerilogRename.scala
deleted file mode 100644
index 4d51128c..00000000
--- a/src/main/scala/firrtl/passes/VerilogRename.scala
+++ /dev/null
@@ -1,11 +0,0 @@
-package firrtl.passes
-import firrtl.ir.Circuit
-import firrtl.transforms.VerilogRename
-
-@deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
-object VerilogRename extends Pass {
- override def run(c: Circuit): Circuit = new VerilogRename().run(c)
- @deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
- def verilogRenameN(n: String): String =
- if (firrtl.Utils.v_keywords(n)) "%s$".format(n) else n
-}