1 files changed, 7 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index fedc4c56..cc74a865 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -8,9 +8,9 @@ import firrtl._
 import firrtl.Utils._
 import MemPortUtils._
 
-object ReplaceMemMacros extends Pass {
+class ReplaceMemMacros(writer: ConfWriter) extends Pass {
 
-  def name = "Replace memories with black box wrappers (optimizes when write mask isn't needed)"
+  def name = "Replace memories with black box wrappers (optimizes when write mask isn't needed) + configuration file"
 
   def run(c: Circuit) = {
 
@@ -57,6 +57,8 @@ object ReplaceMemMacros extends Pass {
       case m: ExtModule => m
     }
 
+    // print conf
+    writer.serialize
     c.copy(modules = updatedMods ++ memMods.toSeq) 
   }  
 
@@ -86,6 +88,9 @@ object ReplaceMemMacros extends Pass {
     //println(wrapper.body.serialize)
 
     val bb = ExtModule(m.info,bbName,bbioPorts) 
+
+    // add to conf file
+    writer.append(m)
     Seq(bb,wrapper)
   }