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-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 4b91d9cd..263422df 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -148,9 +148,9 @@ object MemPortUtils {
def rwPortToBundle(mem: DefMemory) =
BundleType(Seq(
Field("wmode", Default, UIntType(IntWidth(1))),
- Field("data", Default, mem.dataType),
+ Field("wdata", Default, mem.dataType),
Field("rdata", Flip, mem.dataType),
- Field("mask", Default, create_mask(mem.dataType)),
+ Field("wmask", Default, create_mask(mem.dataType)),
Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))),
Field("en", Default, UIntType(IntWidth(1))),
Field("clk", Default, ClockType)))