diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/Checks.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 228 |
1 files changed, 112 insertions, 116 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 23613e65..ebdd2469 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -34,6 +34,7 @@ import scala.collection.mutable.HashMap import scala.collection.mutable.ArrayBuffer import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.Serialize._ @@ -46,7 +47,7 @@ object CheckHighForm extends Pass with LazyLogging { // Custom Exceptions class NotUniqueException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Reference ${name} does not have a unique name.") class InvalidLOCException extends PassException(s"${sinfo}: [module ${mname}] Invalid connect to an expression that is not a reference or a WritePort.") - class NegUIntException extends PassException(s"${sinfo}: [module ${mname}] UIntValue cannot be negative.") + class NegUIntException extends PassException(s"${sinfo}: [module ${mname}] UIntLiteral cannot be negative.") class UndeclaredReferenceException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Reference ${name} is not declared.") class PoisonWithFlipException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Poison ${name} cannot be a bundle type with flips.") class MemWithFlipException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Memory ${name} cannot be a bundle type with flips.") @@ -69,7 +70,7 @@ object CheckHighForm extends Pass with LazyLogging { t map (findFlip) match { case t: BundleType => { for (f <- t.fields) { - if (f.flip == REVERSE) has = true + if (f.flip == Flip) has = true } t } @@ -90,45 +91,45 @@ object CheckHighForm extends Pass with LazyLogging { def checkHighFormPrimop(e: DoPrim) = { def correctNum(ne: Option[Int], nc: Int) = { ne match { - case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.getString, i)) + case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.toString, i)) case None => // Do Nothing } - if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.getString, nc)) + if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.toString, nc)) } e.op match { - case ADD_OP => correctNum(Option(2),0) - case SUB_OP => correctNum(Option(2),0) - case MUL_OP => correctNum(Option(2),0) - case DIV_OP => correctNum(Option(2),0) - case REM_OP => correctNum(Option(2),0) - case LESS_OP => correctNum(Option(2),0) - case LESS_EQ_OP => correctNum(Option(2),0) - case GREATER_OP => correctNum(Option(2),0) - case GREATER_EQ_OP => correctNum(Option(2),0) - case EQUAL_OP => correctNum(Option(2),0) - case NEQUAL_OP => correctNum(Option(2),0) - case PAD_OP => correctNum(Option(1),1) - case AS_UINT_OP => correctNum(Option(1),0) - case AS_SINT_OP => correctNum(Option(1),0) - case AS_CLOCK_OP => correctNum(Option(1),0) - case SHIFT_LEFT_OP => correctNum(Option(1),1) - case SHIFT_RIGHT_OP => correctNum(Option(1),1) - case DYN_SHIFT_LEFT_OP => correctNum(Option(2),0) - case DYN_SHIFT_RIGHT_OP => correctNum(Option(2),0) - case CONVERT_OP => correctNum(Option(1),0) - case NEG_OP => correctNum(Option(1),0) - case NOT_OP => correctNum(Option(1),0) - case AND_OP => correctNum(Option(2),0) - case OR_OP => correctNum(Option(2),0) - case XOR_OP => correctNum(Option(2),0) - case AND_REDUCE_OP => correctNum(None,0) - case OR_REDUCE_OP => correctNum(None,0) - case XOR_REDUCE_OP => correctNum(None,0) - case CONCAT_OP => correctNum(Option(2),0) - case BITS_SELECT_OP => correctNum(Option(1),2) - case HEAD_OP => correctNum(Option(1),1) - case TAIL_OP => correctNum(Option(1),1) + case Add => correctNum(Option(2),0) + case Sub => correctNum(Option(2),0) + case Mul => correctNum(Option(2),0) + case Div => correctNum(Option(2),0) + case Rem => correctNum(Option(2),0) + case Lt => correctNum(Option(2),0) + case Leq => correctNum(Option(2),0) + case Gt => correctNum(Option(2),0) + case Geq => correctNum(Option(2),0) + case Eq => correctNum(Option(2),0) + case Neq => correctNum(Option(2),0) + case Pad => correctNum(Option(1),1) + case AsUInt => correctNum(Option(1),0) + case AsSInt => correctNum(Option(1),0) + case AsClock => correctNum(Option(1),0) + case Shl => correctNum(Option(1),1) + case Shr => correctNum(Option(1),1) + case Dshl => correctNum(Option(2),0) + case Dshr => correctNum(Option(2),0) + case Cvt => correctNum(Option(1),0) + case Neg => correctNum(Option(1),0) + case Not => correctNum(Option(1),0) + case And => correctNum(Option(2),0) + case Or => correctNum(Option(2),0) + case Xor => correctNum(Option(2),0) + case Andr => correctNum(None,0) + case Orr => correctNum(None,0) + case Xorr => correctNum(None,0) + case Cat => correctNum(Option(2),0) + case Bits => correctNum(Option(1),2) + case Head => correctNum(Option(1),1) + case Tail => correctNum(Option(1),1) } } @@ -148,7 +149,7 @@ object CheckHighForm extends Pass with LazyLogging { } def checkValidLoc(e: Expression) = { e match { - case e @ ( _: UIntValue | _: SIntValue | _: DoPrim ) => errors.append(new InvalidLOCException) + case e @ (_: UIntLiteral | _: SIntLiteral | _: DoPrim ) => errors.append(new InvalidLOCException) case _ => // Do Nothing } } @@ -169,7 +170,7 @@ object CheckHighForm extends Pass with LazyLogging { t map (checkHighFormW) } - def checkHighFormM(m: Module): Module = { + def checkHighFormM(m: DefModule): DefModule = { val names = HashMap[String, Boolean]() val mnames = HashMap[String, Boolean]() def checkHighFormE(e: Expression): Expression = { @@ -189,7 +190,7 @@ object CheckHighForm extends Pass with LazyLogging { validSubexp(e.exp) e } - case e: UIntValue => + case e: UIntLiteral => if (e.value < 0) errors.append(new NegUIntException) case e => e map (validSubexp) } @@ -197,7 +198,7 @@ object CheckHighForm extends Pass with LazyLogging { e map (checkHighFormT) e } - def checkHighFormS(s: Stmt): Stmt = { + def checkHighFormS(s: Statement): Statement = { def checkName(name: String): String = { if (names.contains(name)) errors.append(new NotUniqueException(name)) else names(name) = true @@ -209,12 +210,8 @@ object CheckHighForm extends Pass with LazyLogging { s map (checkHighFormT) s map (checkHighFormE) s match { - case s: DefPoison => { - if (hasFlip(s.tpe)) errors.append(new PoisonWithFlipException(s.name)) - checkHighFormT(s.tpe) - } case s: DefMemory => { - if (hasFlip(s.data_type)) errors.append(new MemWithFlipException(s.name)) + if (hasFlip(s.dataType)) errors.append(new MemWithFlipException(s.name)) if (s.depth <= 0) errors.append(new NegMemSizeException) } case s: WDefInstance => { @@ -222,7 +219,7 @@ object CheckHighForm extends Pass with LazyLogging { errors.append(new ModuleNotDefinedException(s.module)) } case s: Connect => checkValidLoc(s.loc) - case s: BulkConnect => checkValidLoc(s.loc) + case s: PartialConnect => checkValidLoc(s.loc) case s: Print => checkFstring(s.string, s.args.length) case _ => // Do Nothing } @@ -243,8 +240,8 @@ object CheckHighForm extends Pass with LazyLogging { } m match { - case m: InModule => checkHighFormS(m.body) - case m: ExModule => // Do Nothing + case m: Module => checkHighFormS(m.body) + case m: ExtModule => // Do Nothing } m } @@ -290,8 +287,8 @@ object CheckTypes extends Pass with LazyLogging { class ValidIfPassiveTypes(info:Info) extends PassException(s"${info}: [module ${mname}] Must validif a passive type.") class ValidIfCondUInt(info:Info) extends PassException(s"${info}: [module ${mname}] A validif condition must be of type UInt.") //;---------------- Helper Functions -------------- - def ut () : UIntType = UIntType(UnknownWidth()) - def st () : SIntType = SIntType(UnknownWidth()) + def ut () : UIntType = UIntType(UnknownWidth) + def st () : SIntType = SIntType(UnknownWidth) def check_types_primop (e:DoPrim, errors:Errors, info:Info) : Unit = { def all_same_type (ls:Seq[Expression]) : Unit = { @@ -322,38 +319,38 @@ object CheckTypes extends Pass with LazyLogging { } e.op match { - case AS_UINT_OP => {} - case AS_SINT_OP => {} - case AS_CLOCK_OP => {} - case DYN_SHIFT_LEFT_OP => is_uint(e.args(1)); all_ground(e.args) - case DYN_SHIFT_RIGHT_OP => is_uint(e.args(1)); all_ground(e.args) - case ADD_OP => all_ground(e.args) - case SUB_OP => all_ground(e.args) - case MUL_OP => all_ground(e.args) - case DIV_OP => all_ground(e.args) - case REM_OP => all_ground(e.args) - case LESS_OP => all_ground(e.args) - case LESS_EQ_OP => all_ground(e.args) - case GREATER_OP => all_ground(e.args) - case GREATER_EQ_OP => all_ground(e.args) - case EQUAL_OP => all_ground(e.args) - case NEQUAL_OP => all_ground(e.args) - case PAD_OP => all_ground(e.args) - case SHIFT_LEFT_OP => all_ground(e.args) - case SHIFT_RIGHT_OP => all_ground(e.args) - case CONVERT_OP => all_ground(e.args) - case NEG_OP => all_ground(e.args) - case NOT_OP => all_ground(e.args) - case AND_OP => all_ground(e.args) - case OR_OP => all_ground(e.args) - case XOR_OP => all_ground(e.args) - case AND_REDUCE_OP => all_ground(e.args) - case OR_REDUCE_OP => all_ground(e.args) - case XOR_REDUCE_OP => all_ground(e.args) - case CONCAT_OP => all_ground(e.args) - case BITS_SELECT_OP => all_ground(e.args) - case HEAD_OP => all_ground(e.args) - case TAIL_OP => all_ground(e.args) + case AsUInt => + case AsSInt => + case AsClock => + case Dshl => is_uint(e.args(1)); all_ground(e.args) + case Dshr => is_uint(e.args(1)); all_ground(e.args) + case Add => all_ground(e.args) + case Sub => all_ground(e.args) + case Mul => all_ground(e.args) + case Div => all_ground(e.args) + case Rem => all_ground(e.args) + case Lt => all_ground(e.args) + case Leq => all_ground(e.args) + case Gt => all_ground(e.args) + case Geq => all_ground(e.args) + case Eq => all_ground(e.args) + case Neq => all_ground(e.args) + case Pad => all_ground(e.args) + case Shl => all_ground(e.args) + case Shr => all_ground(e.args) + case Cvt => all_ground(e.args) + case Neg => all_ground(e.args) + case Not => all_ground(e.args) + case And => all_ground(e.args) + case Or => all_ground(e.args) + case Xor => all_ground(e.args) + case Andr => all_ground(e.args) + case Orr => all_ground(e.args) + case Xorr => all_ground(e.args) + case Cat => all_ground(e.args) + case Bits => all_ground(e.args) + case Head => all_ground(e.args) + case Tail => all_ground(e.args) } } @@ -366,7 +363,7 @@ object CheckTypes extends Pass with LazyLogging { case (t:BundleType) => { var p = true for (x <- t.fields ) { - if (x.flip == REVERSE) p = false + if (x.flip == Flip) p = false if (!passive(x.tpe)) p = false } p @@ -415,15 +412,15 @@ object CheckTypes extends Pass with LazyLogging { if (!passive(tpe(e))) errors.append(new ValidIfPassiveTypes(info)) if (!(tpe(e.cond).typeof[UIntType])) errors.append(new ValidIfCondUInt(info)) } - case (_:UIntValue|_:SIntValue) => false + case (_:UIntLiteral | _:SIntLiteral) => false } e } - def bulk_equals (t1: Type, t2: Type, flip1: Flip, flip2: Flip): Boolean = { + def bulk_equals (t1: Type, t2: Type, flip1: Orientation, flip2: Orientation): Boolean = { //;println_all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2]) (t1,t2) match { - case (t1:ClockType,t2:ClockType) => flip1 == flip2 + case (ClockType, ClockType) => flip1 == flip2 case (t1:UIntType,t2:UIntType) => flip1 == flip2 case (t1:SIntType,t2:SIntType) => flip1 == flip2 case (t1:BundleType,t2:BundleType) => { @@ -444,20 +441,20 @@ object CheckTypes extends Pass with LazyLogging { } } - def check_types_s (s:Stmt) : Stmt = { + def check_types_s (s:Statement) : Statement = { s map (check_types_e(get_info(s))) match { - case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize)) + case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.expr))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize)) case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors.append(new InvalidRegInit(s.info)) - case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize)) + case (s:PartialConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.expr),Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize)) case (s:Stop) => { - if (wt(tpe(s.clk)) != wt(ClockType()) ) errors.append(new ReqClk(s.info)) + if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info)) if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info)) } case (s:Print)=> { for (x <- s.args ) { if (wt(tpe(x)) != wt(ut()) && wt(tpe(x)) != wt(st()) ) errors.append(new PrintfArgNotGround(s.info)) } - if (wt(tpe(s.clk)) != wt(ClockType()) ) errors.append(new ReqClk(s.info)) + if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info)) if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info)) } case (s:Conditionally) => if (wt(tpe(s.pred)) != wt(ut()) ) errors.append(new PredNotUInt(s.info)) @@ -470,8 +467,8 @@ object CheckTypes extends Pass with LazyLogging { for (m <- c.modules ) { mname = m.name (m) match { - case (m:ExModule) => false - case (m:InModule) => check_types_s(m.body) + case (m:ExtModule) => false + case (m:Module) => check_types_s(m.body) } } errors.trigger @@ -486,8 +483,8 @@ object CheckGenders extends Pass { def dir_to_gender (d:Direction) : Gender = { d match { - case INPUT => MALE - case OUTPUT => FEMALE //BI-GENDER + case Input => MALE + case Output => FEMALE //BI-GENDER } } @@ -517,7 +514,7 @@ object CheckGenders extends Pass { val kindx = get_kind(e) def flipQ (t:Type) : Boolean = { var fQ = false - def flip_rec (t:Type,f:Flip) : Type = { + def flip_rec (t:Type,f:Orientation) : Type = { (t) match { case (t:BundleType) => { for (field <- t.fields) { @@ -525,11 +522,11 @@ object CheckGenders extends Pass { } } case (t:VectorType) => flip_rec(t.tpe,f) - case (t) => if (f == REVERSE) fQ = true + case (t) => if (f == Flip) fQ = true } t } - flip_rec(t,DEFAULT) + flip_rec(t,Default) fQ } @@ -564,8 +561,8 @@ object CheckGenders extends Pass { case (e:WSubIndex) => get_gender(e.exp,genders) case (e:WSubAccess) => get_gender(e.exp,genders) case (e:DoPrim) => MALE - case (e:UIntValue) => MALE - case (e:SIntValue) => MALE + case (e:UIntLiteral) => MALE + case (e:SIntLiteral) => MALE case (e:Mux) => MALE case (e:ValidIf) => MALE } @@ -581,18 +578,17 @@ object CheckGenders extends Pass { case (e:DoPrim) => for (e <- e.args ) { check_gender(info,genders,MALE)(e) } case (e:Mux) => e map (check_gender(info,genders,MALE)) case (e:ValidIf) => e map (check_gender(info,genders,MALE)) - case (e:UIntValue) => false - case (e:SIntValue) => false + case (e:UIntLiteral) => false + case (e:SIntLiteral) => false } e } - def check_genders_s (genders:HashMap[String,Gender])(s:Stmt) : Stmt = { + def check_genders_s (genders:HashMap[String,Gender])(s:Statement) : Statement = { s map (check_genders_e(get_info(s),genders)) s map (check_genders_s(genders)) (s) match { case (s:DefWire) => genders(s.name) = BIGENDER - case (s:DefPoison) => genders(s.name) = MALE case (s:DefRegister) => genders(s.name) = BIGENDER case (s:DefNode) => { check_gender(s.info,genders,MALE)(s.value) @@ -602,7 +598,7 @@ object CheckGenders extends Pass { case (s:WDefInstance) => genders(s.name) = MALE case (s:Connect) => { check_gender(s.info,genders,FEMALE)(s.loc) - check_gender(s.info,genders,MALE)(s.exp) + check_gender(s.info,genders,MALE)(s.expr) } case (s:Print) => { for (x <- s.args ) { @@ -611,14 +607,14 @@ object CheckGenders extends Pass { check_gender(s.info,genders,MALE)(s.en) check_gender(s.info,genders,MALE)(s.clk) } - case (s:BulkConnect) => { + case (s:PartialConnect) => { check_gender(s.info,genders,FEMALE)(s.loc) - check_gender(s.info,genders,MALE)(s.exp) + check_gender(s.info,genders,MALE)(s.expr) } case (s:Conditionally) => { check_gender(s.info,genders,MALE)(s.pred) } - case (s:Empty) => false + case EmptyStmt => false case (s:Stop) => { check_gender(s.info,genders,MALE)(s.en) check_gender(s.info,genders,MALE)(s.clk) @@ -635,8 +631,8 @@ object CheckGenders extends Pass { genders(p.name) = dir_to_gender(p.direction) } (m) match { - case (m:ExModule) => false - case (m:InModule) => check_genders_s(genders)(m.body) + case (m:ExtModule) => false + case (m:Module) => check_genders_s(genders)(m.body) } } errors.trigger @@ -654,7 +650,7 @@ object CheckWidths extends Pass { class NegWidthException(info:Info) extends PassException(s"${info}: [module ${mname}] Width cannot be negative or zero.") def run (c:Circuit): Circuit = { val errors = new Errors() - def check_width_m (m:Module) : Unit = { + def check_width_m (m:DefModule) : Unit = { def check_width_w (info:Info)(w:Width) : Width = { (w) match { case (w:IntWidth)=> if (w.width <= 0) errors.append(new NegWidthException(info)) @@ -664,7 +660,7 @@ object CheckWidths extends Pass { } def check_width_e (info:Info)(e:Expression) : Expression = { (e map (check_width_e(info))) match { - case (e:UIntValue) => { + case (e:UIntLiteral) => { (e.width) match { case (w:IntWidth) => if (scala.math.max(1,e.value.bitLength) > w.width) { @@ -674,7 +670,7 @@ object CheckWidths extends Pass { } check_width_w(info)(e.width) } - case (e:SIntValue) => { + case (e:SIntLiteral) => { (e.width) match { case (w:IntWidth) => if (e.value.bitLength + 1 > w.width) errors.append(new WidthTooSmall(info, e.value)) @@ -687,7 +683,7 @@ object CheckWidths extends Pass { } e } - def check_width_s (s:Stmt) : Stmt = { + def check_width_s (s:Statement) : Statement = { s map (check_width_s) map (check_width_e(get_info(s))) def tm (t:Type) : Type = mapr(check_width_w(info(s)) _,t) s map (tm) @@ -698,8 +694,8 @@ object CheckWidths extends Pass { } (m) match { - case (m:ExModule) => {} - case (m:InModule) => check_width_s(m.body) + case (m:ExtModule) => {} + case (m:Module) => check_width_s(m.body) } } |