1 files changed, 13 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/MinimumVerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/MinimumVerilogEmitter.scala
new file mode 100644
index 00000000..4d8bade6
--- /dev/null
+++ b/src/main/scala/firrtl/backends/verilog/MinimumVerilogEmitter.scala
@@ -0,0 +1,13 @@
+package firrtl
+
+import firrtl.stage.TransformManager
+
+class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
+
+  override def prerequisites = firrtl.stage.Forms.AssertsRemoved ++
+    firrtl.stage.Forms.LowFormMinimumOptimized
+
+  override def transforms =
+    new TransformManager(firrtl.stage.Forms.VerilogMinimumOptimized, prerequisites).flattenedTransformOrder
+
+}