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Diffstat (limited to 'spec/spec.tex')
| -rw-r--r-- | spec/spec.tex | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/spec/spec.tex b/spec/spec.tex index 93d62525..12f2c91e 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -1792,18 +1792,22 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio %\section{TODO} % %- FIRRTL implementation -% - Make register reset/init optional ; good % - Rework readwrite port types ; limits optimizations but probably ok -% - Add memory read-under-write flag ; probably overengineering, but could be a wash +% - Make register reset/init optional ; good +% - removed addw, added head and tail ; great! +% - Add UBits ; andrew doesn't care, favors overloading UInt +% - Add SBits % - Add partial connect algorithm ; % - Add oriented types to type checker +% - Add memory read-under-write flag ; probably overengineering, but could be a wash +% - *FINISHED* Add Mux expression ; that's lovely, need glitch-free mux for clock types +% - *FINISHED* add rename pass for verilog % - *FINISHED* Add is invalid ; good % - *FINISHED* Add validif ; good -% - Add UBits ; andrew doesn't care, favors overloading UInt -% - Add SBits -% - *FINISHED* Add Mux expression ; that's lovely, need glitch-free mux for clock types -% - removed addw, added head and tail ; great! -% - add rename pass for verilog + +%- Proposed changes to spec +% - switch back to precise dynamic left shift +% - have a wmode instead of rmode for readwrite ports \end{document} |