diff options
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 15 |
1 files changed, 14 insertions, 1 deletions
@@ -7,9 +7,9 @@ on-reset Parser Error if incorrectly assign stuff, like use = instead of := Update parser and update tests -Change all primops to be strict on data widths Make instances always male, flip the bundles on declaration dlsh,drsh +move Infer-Widths to before vec expansion? ======== Update Core ========== Add source locaters @@ -25,13 +25,22 @@ Well-formed high firrtl Subfields are only on bundles, before type inference Can only connect to a Ref or Subfield or Index UInt only has positive ints + No combinational loops + cannot connect to a pad, or a register. only connct to a reference After adding dynamic assertions, insert bounds check with accessor expansion Well-formed low firrtl All things only assigned to once +Width inference + No names + No Unknowns + All widths are positive + Pad's width is greater than value's width + pad's width is greater than value's width ======== Other Passes ======== constant folding (partial eval) pass common subexpression elimination pass +Verilog backend ======== Consultations ======== Stephen: @@ -52,6 +61,10 @@ Figure out how widths propogate for all updated primops (Adam) Add partial bulk connect (Scott, Stephen) Add FIFOs to the IR (Palmer) Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed) +Union Types +Enums? +Convert to scala +Firrtl interpreter (in scala) ======== Update Spec ======== Add Not to spec |