diff options
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 22 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 8e278120..f62e4f86 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -308,6 +308,7 @@ object CheckTypes extends Pass with LazyLogging { class IndexNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Index is not of UIntType.") class EnableNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Enable is not of UIntType.") class InvalidConnect(info:Info) extends PassException(s"${info}: [module ${mname}] Type mismatch.") + class InvalidRegInit(info:Info) extends PassException(s"${info}: [module ${mname}] Type of init must match type of DefRegister.") class PrintfArgNotGround(info:Info) extends PassException(s"${info}: [module ${mname}] Printf arguments must be either UIntType or SIntType.") class ReqClk(info:Info) extends PassException(s"${info}: [module ${mname}] Requires a clock typed signal.") class EnNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Enable must be a UIntType typed signal.") @@ -479,6 +480,7 @@ object CheckTypes extends Pass with LazyLogging { def check_types_s (s:Stmt) : Stmt = { s map (check_types_e(get_info(s))) match { case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors += new InvalidConnect(s.info) + case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors += new InvalidRegInit(s.info) case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp)) ) errors += new InvalidConnect(s.info) case (s:Stop) => { if (wt(tpe(s.clk)) != wt(ClockType()) ) errors += new ReqClk(s.info) diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index eda5d5d2..64f71180 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -27,4 +27,26 @@ class UnitTests extends FlatSpec with Matchers { } } } + + "Initializing a register with a different type" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + CheckHighForm, + ResolveKinds, + InferTypes, + CheckTypes) + val input = + """circuit Unit : + | module Unit : + | input clk : Clock + | input reset : UInt<1> + | wire x : { valid : UInt<1> } + | reg y : { valid : UInt<1>, bits : UInt<3> }, clk with : + | reset => (reset, x)""".stripMargin + intercept[PassExceptions] { + passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + } } |