diff options
| -rw-r--r-- | test/passes/expand-accessors/accessor-vec.fir | 30 | ||||
| -rw-r--r-- | test/passes/expand-accessors/simple.fir | 5 | ||||
| -rw-r--r-- | test/passes/expand-accessors/simple2.fir | 5 |
3 files changed, 24 insertions, 16 deletions
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index 1d1bbec9..8b4b7eb8 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -1,9 +1,13 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Accessors circuit top : module top : wire m : UInt<32>[2][2][2] + wire a : UInt<32>[2][2] + wire b : UInt<32>[2] + wire c : UInt<32> + wire i : UInt + wire j : UInt m[0][0][0] <= UInt(1) m[1][0][0] <= UInt(1) m[0][1][0] <= UInt(1) @@ -12,36 +16,38 @@ circuit top : m[1][0][1] <= UInt(1) m[0][1][1] <= UInt(1) m[1][1][1] <= UInt(1) - wire i : UInt i <= UInt(1) - infer accessor a = m[i] ;CHECK: indexer a = (m[0] m[1])[i] : UInt<32>[2][2] - infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] - infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> - wire j : UInt + a <= m[i] + b <= a[i] + c <= b[i] j <= c - infer accessor x = m[i] ;CHECK: indexer (m[0] m[1])[i] = x : UInt<32>[2][2] + wire x : UInt<32>[2][2] + wire y : UInt<32>[2] + wire z : UInt<32> x[0][0] <= UInt(1) x[1][0] <= UInt(1) x[0][1] <= UInt(1) x[1][1] <= UInt(1) - infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] - infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> y[0] <= UInt(1) y[1] <= UInt(1) + m[i] <= x + x[i] <= y + y[i] <= z z <= j wire p : {n : UInt<32>[2]} p.n[0] <= UInt(1) p.n[1] <= UInt(1) - infer accessor q = p.n[i] ;CHECK: indexer (p.n[0] p.n[1])[i] = q : UInt<32> + wire q : UInt<32> + p.n[i] <= q q <= j wire r : {m : UInt<32>}[2] r[0].m <= UInt(1) r[1].m <= UInt(1) - infer accessor s = r[i] ;CHECK: indexer s = (r[0] r[1])[i] : { m : UInt<32>} + wire s : { m : UInt<32>} + s <= r[i] j <= s.m -; CHECK: Finished Expand Accessors ; CHECK: Done! diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir index 7e8a4dcd..b595fc4c 100644 --- a/test/passes/expand-accessors/simple.fir +++ b/test/passes/expand-accessors/simple.fir @@ -1,6 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Accessors +;CHECK: Done! circuit top : module top : output o : UInt @@ -9,7 +9,8 @@ circuit top : m[0] <= UInt("h1") m[1] <= UInt("h1") i <= UInt("h1") - infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> + wire a : UInt<32> + a <= m[i] o <= a diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir index 550d34b8..a7d8258d 100644 --- a/test/passes/expand-accessors/simple2.fir +++ b/test/passes/expand-accessors/simple2.fir @@ -1,6 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Accessors +;CHECK: Done! circuit top : module top : output o1 : UInt @@ -10,7 +10,8 @@ circuit top : m[0] <= UInt("h1") m[1] <= UInt("h1") i <= UInt("h1") - infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> + wire a : UInt<32> + a <= m[i] o1 <= a o2 <= a |